Semiconductor memory device with refresh trigger

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cell transistors;
• an X decoder designating a position of an X axis of the memory cell;
• a Y decoder designating a position of a Y axis crossing the X axis;
• a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder and the Y decoder;
• a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source;
• a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information;
• and
• an operational amplifier receiving a refresh signal from the refresh trigger circuit, and making operations of read, write and erase of the memory cell transistors.