Semiconductor memory device

A semiconductor memory device comprising:

• a sense amplifier;
• a plurality of memory cell arrays;
• shared MOS transistors selecting one of the memory cell arrays arranged on both sides of the sense amplifier;
• and
• a control circuit controlling operation of the shared MOS transistors,
• wherein the control circuit performs control of setting gate voltages of the shared MOS transistors to second potential between first potential of a word line boosting power source and ground potential in a standby state, setting the gate voltages of the shared MOS transistors in a non-selected memory cell array side to the ground potential after command input, setting the gate voltages of the shared MOS transistors in a selected memory cell array side from the second potential to the first potential when re-coupling the memory cell arrays and the sense amplifier and returning gate voltages of a selected side shared MOS transistor and a non-selected side shared MOS transistor to the second potential again in a standby.