Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values

A charge sharing circuit for first and second pairs of complementary signal lines comprising:

• a capacitor coupled between first and second circuit nodes;
• a first circuit coupled between a supply voltage source and a reference voltage level and coupled to first ones of said first and second pairs of complementary signal lines and said first circuit node;
• a second circuit coupled between said supply voltage source and said reference voltage level and coupled to second ones of said first and second pairs of complementary signal lines and said second circuit node;
• a third circuit coupled between said first ones of said first and second pairs of complementary signal lines and to said second circuit node;
• and
• a fourth circuit coupled between said second ones of said first and second pairs of complementary signal lines and to said first circuit nodes
• wherein said first and second pairs of complementary signal lines comprise local and global data read lines in an integrated circuit memory array.

A data read driver for an integrated circuit memory array comprising:

• a first transistor responsive to a data read signal for coupling a supply voltage to a local data read line;
• a second transistor responsive to a global clock signal for coupling a reference voltage level to a global data read line;
• and
• a charge sharing circuit coupled between said local data read line and said global data read line comprising a capacitor coupled between first and second circuit nodes, first and second switching devices for respectively coupling said first and second circuit nodes to said local data read line, and third and fourth switching devices for respectively coupling said first and second circuit nodes to said global data read line.

A charge sharing method comprising:

• providing a capacitor having first and second terminals thereof;
• firstly coupling a first signal line to said first terminal of said capacitor and coupling a second signal line to said second terminal of said capacitor;
• firstly decoupling said first and second signal lines from said first and second terminals of said capacitor respectively;
• secondly coupling said first signal line to said second terminal of said capacitor and coupling said second signal line to said first terminal of said capacitor;
• secondly decoupling said first and second signal lines from said second and first terminals of said capacitor respectively;
• and
• repeating said process of firstly coupling, firstly decoupling, secondly coupling and secondly decoupling.