US 7,609,565 B2 · External clock tracking pipelined latch scheme

Abstract

A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second command latch input, and a command latch output, the first command latch input to couple to the command decoder output, and the second command latch input to couple to a write command output of an internal clock control generator; and a command register including a first command register input and a second command register input, the first command register input to couple to the command latch output, and the second command register input to couple to an internal latch command output of the internal clock control generator. Additional apparatus, systems, and methods are disclosed.

Claims23

Dependent claims

A flash memory comprising:

an internal clock control generator including a first input to receive an externally generated write enable signal, and a first output operable to provide an internally generated write enable signal that tracks the externally generated write enable signal by providing an internally generated write enable clock pulse at some time after a given signal level transition at the first input and before the next consecutive same signal level transition at the first input,
the internal clock control generator including a tracking circuit, the tracking circuit including a resettable pulse generator coupled to a second pulse generator, the resettable pulse generator having an input coupled to the first input and including a resettable pulse generator output coupled to a node, the second pulse generator including an input coupled to the node and a second pulse generator output coupled to the first output.

A method comprising:

receiving at an input to a flash memory an externally generated write enable signal including a sequence of a plurality of signal level transitions from a first signal level to a second signal level;
generating, in response to each of the plurality of signal level transitions, an internally generated write enable signal pulse that tracks the particular one of the plurality of signal level transitions that the internally generated write enable signal pulse is being generated in response to,
wherein generating the internally generated write enable signal pulse includes generating a pulse having a predetermined pulse width occurring for a time duration and as long as the state of the externally generated write enable signal remains at the second signal level during the time duration of the predetermined pulse width.

A system comprising:

a processor;
a flash memory coupled to the processor, the flash memory including a set of pipelined latches including at least one command latch coupled to a data input, at least one address latch coupled to the data input, and at least one data latch coupled to the data input;
and
an internal clock control generator coupled to a first input including an externally generated write enable signal input, the internal clock control generator coupled to the at least one command latch, to the at least one address latch, and to the at least one data latch,
the internal clock control generator including a tracking circuit including a resettable pulse generator having an input coupled to the externally generated write enable signal input and having a resettable pulse generator output coupled to a node, and a second pulse generator having an input coupled to the node and having a second pulse generator output operable to provide internally generated write enable clock pulses that track each of a plurality of externally generated write enable signal pulses received at the input to the internal clock control generator,
wherein each of the internally generated write enable clock pulses track a particular one of the externally generated write enable signal pulses.

3 more elements

Dependencies are inferred from the claim text.

External clock tracking pipelined latch scheme

Life of this patent

External clock tracking pipelined latch scheme

Life of this patent

Abstract

Claims23