Sensing of memory cells in a solid state memory device by fixed discharge of a bit line
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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Abstract
In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to which the target memory cell is coupled. A fixed unit of charge is removed from the charged bit line. The bit line is sensed by sense amplifiers to determine the read voltage (i.e., threshold voltage) applied to a word line coupled to the target cell in order to turn on the target cell. The threshold voltage is indicative of the analog voltage stored on the target memory cell.
Claims18
A method for sensing of a target memory cell, the method comprising:
- charging a series string of memory cells coupled to the target memory cell by clocking a select gate drain transistor with a clocking signal coupled to a control gate of the transistor such that the transistor turns on and off in response to the clocking signal;
- discharging the series string by a fixed unit of charge after the series string is charged;
- and
- sensing a current on the bit line in response to the target memory cell turning on.
A method for operating a memory device, the method comprising:
- programming, to a first voltage level, a target memory cell of a series string of memory cells coupled to a bit line;
- verifying that the target memory cell is programmed to the first voltage level;
- and
- sensing the target memory cell by:
- precharging the bit line to a second voltage level;
- charging the series string to the bit line;
- discharging the series string by a fixed quantity of charge/discharge cycles;
- and
- sensing a current on the bit line in response to a read voltage applied to a word line coupled to the target memory cell.
A solid state memory device comprising:
- an array of memory cells organized in rows of memory cells coupled to word lines and series strings of memory cells coupled to bit lines;
- control circuitry for the array of memory cells wherein the control circuitry is adapted to sense a current on a bit line coupled to a target memory cell, in order to determine a representative analog voltage programmed into the target memory cell, by transferring a charge from the bit line to a series string of memory cells comprising the target memory cell then removing a fixed unit of charge from the bit line;
- and
- a read/write channel coupled between the control circuitry and the array of non-volatile memory cells, the read/write channel having digital-to-analog conversion circuitry and analog-to-digital conversion circuitry.
Dependencies are inferred from the claim text.