Non-volatile semiconductor memory device

A non-volatile semiconductor memory device comprising:

• a memory cell array having a plurality of electrically-programmable memory cells, each of said memory cells being a multi-level cell to be programmed to have a threshold voltage among three or more threshold voltage distributions, said memory cell array comprising,
• a plurality of memory cell units, each memory cell unit including memory cells connected in series, each memory cell unit being connected to a source selection gate transistor at one end and to a drain selection gate transistor at the other end,
• a plurality of word lines each connected to each of control gates of said memory cells, said plurality of word lines including a selected word line connected to a control gate of a selected memory cell to be programmed to raise the threshold voltage by applying to said selected word line a positive potential enough to turn on said selected memory cell, and a plurality of non-selected word lines except for said selected word line;
• a plurality of bit lines each connected to said drain selection gate transistor of each of said plurality of said memory cell units;
• and
• a source line commonly connected to the source side of said source selection gate transistor of each of said memory cell units,
• wherein a potential applied to a non-selected word line adjacent to said selected word line at time of programming said selected memory cell having a threshold voltage higher than a predetermined voltage is higher than a potential applied to said non-selected word line adjacent to said selected word line at time of programming said selected memory cell having a threshold voltage lower than a predetermined voltage.

A non-volatile semiconductor memory device comprising:

• a memory cell array having a plurality of electrically-programmable memory cells, each of said memory cells being a multi-level cell having a single floating gate, the threshold voltage of said memory cell increasing according to the amount of charges in said single floating gate, said threshold voltage corresponding to a combination of a lower page bit and a upper page bit, said memory cell array comprising,
• a plurality of memory cell units, each memory cell unit including memory cells connected in series, each memory cell unit being connected to a source selection gate transistor at one end and to a drain selection gate transistor at the other end,
• a plurality of word lines each connected to each of control gates of said memory cells, said plurality of word lines including a selected word line connected to a control gate of a selected memory cell to be programmed by applying to said selected word line positive potentials enough to turn on said selected memory cell, and a plurality of non-selected word lines except for said selected word line;
• a plurality of bit lines each connected to said drain selection gate transistor of each of said plurality of said memory cell units;
• and
• a source line commonly connected to said source selection gate transistor of each of said memory cell units,
• wherein a potential applied to a non-selected word line adjacent to said selected word line at time of programming said upper page bit of said selected memory cell are higher than potentials applied to said non-selected word line adjacent to said selected word line at time of programming said lower page bit of said selected memory cell.