US 7,609,556 B2Granted

Non-volatile memory with improved program-verify operations

AssigneeSanDisk Corporation

InventorSiu Lung Chan

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Abstract

In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

Claims8

Dependent claims

A non-volatile memory, comprising:

an array of memory cells to be programmed relative to a demarcation threshold voltage;
a programming circuit for applying a programming pulse to the group of memory cells;
a sensing circuit with a first configuration to verify the cells of the group relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage;
a memory controller alternately controlling applying a programming pulse and verifying the programmed result for the group of memory cells in parallel;
said verifying further comprises:
a first verifying relative to a first reference threshold voltage at a predetermined margin below that of the demarcation threshold voltage;
reducing the rate of subsequent programming of the cell that has been verified relative to the first reference threshold voltage;
a second verifying relative to the demarcation threshold voltage;
and
inhibiting the memory cell that has been verified relative to the demarcation threshold voltage from further programming;
and wherein:
said second verifying is skipped until at least one of the memory cells of the group has been verified relative to the first threshold voltage.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/955,624Filed 13 Dec 2007 · division
Priority: 29 Dec 2005
Published: US 2008/0094911 A124 Apr 2008
Granted: 27 Oct 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…
G11C 8/12
Arrangements for selecting an address in a digital store: group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Family

Application11/323,577Parent of this division · filed 29 Dec 2005
US 2008/0094911 A1Pre-grant publication · published 24 Apr 2008
US 7,310,255 B2Parent of this division
US 2007/0171725 A1Published application
US 7,609,556 B2This patent

From the US filing history. Foreign family members aren’t listed.

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