NAND flash memory device with burst read latency function

A memory system comprising a NAND flash memory device, and a memory controller which outputs a read enable signal to the NAND flash memory device during a read operation and which takes data from the NAND flash memory device after a burst latency time passed, wherein the NAND flash memory device comprises:

• an interface block which receives the read enable signal to output an internal clock signal;
• a buffer clock controlling circuit which operates in response a data output enable signal and the internal clock signal;
• a buffer clock generating circuit which receives the internal clock signal and which generates first and second buffer clock signals according to a control output of the buffer clock controlling circuit;
• and
• a data output buffer circuit which sequentially outputs read data in response to one of the first and second buffer clock signals.

A NAND flash memory device comprising:

• an interface block which receives an external read enable signal during a read operation to output an internal clock signal;
• a buffer clock controlling circuit which activates a clock enable signal in response to a first high-to-low transition of the internal clock signal when a data output enable signal is activated;
• a first clock generator which generates a first buffer clock signal in response to the clock enable signal and a lock flag signal which indicates whether a first clock signal has zero phase difference with respect to the internal clock signal;
• a second clock generator which generates a second buffer clock signal in response to the data output enable signal, the internal clock signal, and the lock flag signal;
• a selection circuit which selects one of the first buffer clock signal and the second buffer clock signal according to a control output of the buffer clock controlling circuit;
• and
• a data output buffer circuit which sequentially outputs read data in response to the buffer clock signal selected by the selection circuit,
• wherein the second buffer clock generating circuit generates the second buffer clock signal having a single pulse when the data output enable signal is activated, and
• wherein the first buffer clock generating circuit generates the first buffer clock signal having zero phase difference with respect to the internal clock signal after the external read enable signal is inputted, and a burst read latency time has passed.