Non-volatile multilevel memory cell programming

A memory device comprising:

• an array of multilevel memory cells having a number of lower pages and an upper page of data associated therewith;
• and
• control circuitry coupled to the array and configured to:
• program a first lower page of a first group of cells of a first wordline, wherein each of the cells has an initial negative threshold voltage level corresponding to an erase state;
• subsequently program a second and a third lower page and an upper page of the cells of the first group, wherein at least one of the first, second, and third lower page and the upper page programming includes:
• applying a number of programming voltage pulses to a control gate of each of the cells of the first group until each of the cells of the first group has reached a positive threshold voltage (Vt) level of a number of positive Vt levels each corresponding to a different data state.

A method for programming an array of non-volatile multilevel memory cells to a number of different threshold voltage (Vt) levels corresponding to different data states, the method comprising:

• programming a lower page of a first wordline cell to increase a Vt of the first wordline cell to a first lowermost Vt level;
• programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell;
• and
• programming the upper page of the first wordline cell such that the Vt of the first wordline cell is increased to a second lowermost Vt level, wherein the second lowermost Vt level is positive.