Multivalue memory storage with two gating transistors

A method of detecting a plurality of data bits stored in a multivalue memory cell, the method comprising:

• activating, by memory control circuitry, both a first gating transistor of the multivalue memory cell and a second gating transistor of the multivalue memory cell, wherein the first gating transistor is coupled to a first bit line, and wherein the second gating transistor is coupled to a second bit line;
• comparing, by sensing circuitry, a first reference voltage to a first bit-line voltage of the first bit line;
• comparing, by the sensing circuitry, a second reference voltage to the first bit-line voltage;
• and
• comparing, by the sensing circuitry, a third reference voltage to a second bit-line voltage of the second bit line, wherein the first reference voltage and the second reference voltage differ.

A system, comprising:

• a digital memory device including:
• a plurality of multilevel memory cells, at least one multivalue memory cell comprising a first gating transistor, a second gating transistor, and a storage element, wherein the storage element is coupled to both the first gating transistor and the second gating transistor;
• a first bit line coupled to the first gating transistor;
• a second bit line coupled to the second gating transistor;
• and
• sensing circuitry coupled to both the first bit line and the second bit line, wherein the sensing circuitry is configured to:
• compare a first bit-line voltage, driven to the first bit line, to a first reference voltage;
• compare the first bit-line voltage to a second reference voltage, wherein the first reference voltage and the second reference voltage are different;
• and
• compare a second bit-line voltage, driven to the second bit line, to a third reference voltage;
• and
• a memory controller coupled to the digital memory device via a data bus and configured to read and write data from the memory device via the memory bus.

An apparatus, comprising:

• means for activating first and second gating transistors of a multivalue memory cell, wherein the first and second gating transistors are coupled to a storage node of the multivalue memory cell;
• and
• means for comparing:
• a first reference voltage to a first bit-line voltage of the first bit line;
• a second reference voltage to the first bit-line voltage, wherein the first reference voltage and the second reference voltage are different;
• and
• a third reference voltage to a second bit-line voltage of the second bit line.