Memory cells with lower power consumption during a write operation

A memory array, comprising:

• a plurality of memory cells organized in row and columns, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line;
• and wherein each of the memory cells comprises:
• a first inverter having an input terminal coupled to a first storage node, an output terminal coupled to a second storage node, a first power supply voltage terminal for receiving a first power supply voltage, and a ground terminal;
• a second inverter having an input terminal coupled to the output terminal of the first inverter at the second storage node, an output terminal coupled to the input terminal of the first inverter at the first storage node, a second power supply voltage terminal, and a third power supply voltage terminal;
• and
• a read port coupled to one of the first or the second storage nodes;
• a first power supply conductor, coupled to the second power supply voltage terminals of each of the plurality of memory cells in a column of memory cells, the first power supply conductor traversing the memory array in a direction parallel to the column of memory cells;
• and
• a second power supply conductor, coupled to the third power supply voltage terminals of each of the plurality of memory cells in a row of memory cells, the second power supply conductor traversing the memory array in a direction parallel to the row of memory cells, wherein both of the second and third power supply voltage terminals receive power supply voltages that are independently variable with respect to the first power supply voltage during a write operation to each of the plurality of memory cells.

A method for writing to a memory cell, the memory cell comprising a first inverter and a second inverter, the first inverter having an input terminal coupled to a first storage node and an output terminal coupled to a second storage node, the second inverter having an input terminal coupled to the second storage node and an output terminal coupled to the first storage node, the method comprising:

• providing a first power supply voltage at a first potential to a first power supply voltage terminal of the second inverter;
• providing a second power supply voltage at a second potential to a second power supply voltage terminal of the second inverter;
• lowering the first power supply voltage;
• raising the second power supply voltage;
• coupling the first storage node to a bit line;
• returning the first power supply voltage to the first potential;
• returning the second power supply voltage to the second potential;
• and
• decoupling the first storage node from the bit line.

A method for writing to a memory cell, the memory cell comprising a first inverter and a second inverter, the first inverter having an input terminal coupled to a first storage node and an output terminal coupled to a second storage node, the second inverter having an input terminal coupled to the second storage node and an output terminal coupled to the first storage node, a read port coupled to one of the first or second storage nodes, the method comprising:

• providing a first power supply voltage at a first potential to a first power supply voltage terminal of the second inverter;
• providing a second power supply voltage at a second potential to a second power supply voltage terminal of the second inverter but not to the first inverter;
• lowering the first power supply voltage;
• coupling the first storage node to a bit line;
• returning the first power supply voltage to the first potential;
• and
• decoupling the first storage node from the bit line.