Logic process DRAM

An apparatus for reducing noise and overall bit line capacitance in a dynamic random access memory (DRAM) device, comprising:

• a plurality of pairs of bit line means for conducting electrical signals,
• wherein each pair of bit line means includes a first bit line means and a second bit line means,
• wherein the first bit line means and the second bit line means within each pair of bit line means are aligned adjacent to each other;
• a plurality of word line means,
• wherein each word line means is associated with the bit line means such that an array is formed by the bit line means and the associated word line means;
• a first interconnect layer means and a second interconnect layer means, wherein each bit line means within each pair of bit line means is associated with both the first and second interconnect layer means;
• a plurality of means for storing data,
• wherein each of the plurality of means for storing data is associated with every other bit line means along each word line means;
• and
• a plurality of means for amplifying,
• wherein each of the plurality of means for amplifying is in communication with a first bit line means and a second bit line means within a pair of bit line means.

A method of reducing noise and overall bit line capacitance in a dynamic random access memory (DRAM) device, the DRAM device including a plurality of bit line pairs, a plurality of word lines, a plurality of memory cells, a first interconnect layer and a second interconnect layer, and a plurality of amplifiers, wherein each bit line pair includes a first bit line and a second bit line, the method comprising the steps of associating each of the bit lines with both the first and second interconnect layers;

• aligning the first bit line and the second bit line within each bit line pair to be adjacent to each other;
• associating each word line with the bit lines such that an array is formed by the bit lines and the associated word lines;
• associating each of the plurality of memory cells with every other bit line along each word line;
• and
• bringing each of the plurality of amplifiers into communication with a first bit line and a second bit line within a bit line pair.