Driving apparatus for liquid crystal display

A driving apparatus for a liquid crystal display, comprising:

• an image signal processor for separating a television image signal from a complex image signal and for separating a complex synchronizing signal;
• a liquid crystal display panel for displaying the television image signal;
• a variable circuit connected to a source start pulse generator of a timing controller for generating a variable signal delayed from one of a frequency-dividing clock signal and a horizontal synchronizing signal from the timing controller for adjusting a display start time of the television image signal displayed on the liquid crystal display panel by a user and supplying the delayed one to the source start pulse generator of the timing controller;
• the source start pulse generator for generating a source start pulse determining a display start time of the television image signal displayed on the liquid crystal display panel using the variable signal from variable circuit and the complex synchronizing signal;
• and
• a phase locked loop control circuit for generating a phase locked loop and applying the phase locked loop to the timing controller.

A flat panel display device, comprising:

• an image signal processor for separating a video image signal from a complex image signal and for separating a complex synchronizing signal;
• a display panel for displaying the video image signal;
• a variable circuit connected to a source start pulse generator of a timing controller for generating a variable signal delayed from one of a frequency-dividing clock signal and a horizontal synchronizing signal from the timing controller for adjusting a display start time of the video image signal displayed on the display panel by a user and supplying the delayed one to the source start pulse generator of the timing controller;
• the source start pulse generator for generating a source start pulse determining a display start time of the video image signal displayed on the display panel using the variable signal from variable circuit and the complex synchronizing signal;
• and
• a phase locked loop control circuit for generating a phase locked loop and applying the phase locked loop to the timing controller.