Pixel load instruction for a programmable graphics processor
AssigneeNVIDIA Corporation
InventorWalter E. Donovan
Life of this patent
Estimating the term…
Abstract
A pixel load instruction for a programmable graphics processor. The pixel load instruction may be used during processing of graphics data to load graphics data from a writable output buffer into a local storage element. Using the pixel load instruction may ensure that the graphics data loaded is current, i.e., any pending writes to the location storing the graphics data are completed prior to loading the graphics data. Furthermore, the pixel load instruction may be enabled and disabled for one or more writable output buffers by setting or clearing bits in a pixel load enable register.
Claims22
A pixel load unit residing within a texture unit and configured for detecting pixel collisions during fragment shading, comprising:
- a first coverage data buffer;
- a second coverage data buffer;
- and
- a pixel collision detector coupled to the first coverage data buffer and coupled to the second coverage data buffer, wherein the pixel collision detector configures the first coverage data buffer to be readable and non-writable and configures the second coverage data buffer to be readable and writable, and the pixel collision detector is further configured to detect pixel collisions occurring when multiple fragments associated with a same position in an output buffer in graphics memory undergo fragment shading, wherein the same position includes X and Y coordinates, and to output a sync bundle when a collision is detected in the second coverage data buffer.
A method implemented by a pixel load unit for detecting a collision between a first fragment and a second fragment when processing fragments in a fragment processing unit, the method comprising:
- configuring a first coverage data buffer within the pixel load unit to be readable and non-writable;
- configuring a second coverage data buffer within the pixel load unit to be readable and writable;
- receiving the first fragment, which is associated with a position in an output buffer that includes X and Y coordinates;
- detecting a collision between the first fragment and the second fragment in the second coverage data buffer;
- and
- outputting a sync bundle to a raster analyzer when the collision is detected in the second coverage data buffer.
A programmable graphics processor for multithreaded execution of program instructions comprising:
- a read interface configured to read data from a graphics memory;
- fragment processing units configured to process fragments associated with at least one position in an output array resident in the graphics memory, the position including X and Y coordinates, wherein each fragment processing unit includes a pixel load unit that includes a pixel collision detector coupled to a first coverage data buffer and to a second coverage data buffer, wherein the pixel collision detector configures the first coverage data buffer to be readable and non-writable and configures the second coverage data buffer to be readable and writable, and wherein each fragment processing unit is configured to store the position associated with each fragment in the second coverage data buffer, detect the occurrence of multiple fragments associated with a same position in the output array, and generate a position conflict status, and output a sync bundle when a collision is detected in the second coverage data buffer;
- and
- a write interface configured to write the processed fragments to the graphics memory.
Dependencies are inferred from the claim text.