Circuit for converting a voltage range of a logic signal

A circuit to convert a first logic signal having a first range to a pair of complementary second logic signals having a second range, comprising:

• a first transistor to selectively couple a first output node to a first reference voltage when the first output node is to be in a first state;
• a resistor coupled to a second reference voltage;
• a second transistor to selectively discharge the first output node toward the second reference voltage via the resistor when the first output node is to transition from the first state to a second state, the second state being a logical complement of the first state;
• a first source-follower circuit having a source follower output coupled to the first output node;
• a third transistor to selectively couple a second output node to the first reference voltage when the second output node is to be in the first state;
• a fourth transistor to selectively discharge the second output node toward the second reference voltage via the resistor when the second output node is to transition from the first state to the second state;
• a second source-follower circuit having a source follower output coupled to the second output node;
• a dynamic current source having a control input coupled to the resistor;
• a fifth transistor to selectively couple the source follower output of the first source follower circuit to the dynamic current source when the first output node is to be in the second state;
• and
• a sixth transistor to selectively couple the source follower output of the second source-follower circuit to the dynamic current source when the second output node is to be in the second state.

A circuit to convert a first logic signal having a first range to at least one second logic signal having a second range, comprising:

• a first p-channel metal oxide semiconductor (PMOS) transistor having a gate coupled to a first control signal, a source coupled to a first reference voltage, and a drain coupled to a first output node;
• a resistor coupled to a second reference voltage;
• a second PMOS transistor having a gate coupled to a second control signal, the second control signal being a logical complement of the first control signal, the second PMOS transistor having a source coupled to the first output node and a drain coupled to the resistor;
• a first n-channel metal oxide semiconductor (NMOS) transistor having a gate coupled to a bias voltage, a source coupled to the first output node, and a drain coupled to the first reference voltage;
• a dynamic current source having a control input coupled to the resistor;
• and
• a second NMOS transistor having a gate coupled to the first control signal, a source coupled to the dynamic current source, and a drain coupled to the first output node;
• wherein a steady-state voltage of the first output node when the first control signal is HIGH is a voltage within the range 100 millivolts and 350 millivolts, inclusive.

A cell of a current steering digital-to-analog converter, comprising:

• a cell current source;
• a first transistor coupled in series with the current source and coupled to a current summing line;
• a second transistor coupled in series with the cell current source and coupled to a reference node;
• a driver circuit having an input, a first output coupled to a gate of the first transistor, and a second output coupled to a gate of the second transistor;
• wherein the driver circuit comprises:
• a third transistor to selectively couple the first output of the driver circuit to a first reference voltage when the first output of the driver circuit is to be in a first state;
• a resistor coupled to a second reference voltage;
• a fourth transistor to selectively discharge the first output of the driver circuit toward the second reference voltage via the resistor when the first output of the driver circuit is to transition from the first state to a second state, the second state being a logical complement of the first state;
• a first source-follower circuit having a source follower output coupled to the first output of the driver circuit;
• a fifth transistor to selectively couple the second output of the driver circuit to the first reference voltage when the second output of the driver circuit is to be in the first state;
• a sixth transistor to selectively discharge the second output of the driver circuit toward the second reference voltage via the resistor when the second output of the driver circuit is to transition from the first state to the second state;
• a second source-follower circuit having a source follower output coupled to the second output of the driver circuit;
• a dynamic current source having a control input coupled to the resistor;
• a seventh transistor to selectively couple the source follower output of the first source follower circuit to the dynamic current source when the first output of the driver circuit is to be in the second state;
• and
• an eighth transistor to selectively couple the source follower output of the second source-follower circuit to the dynamic current source when the second output of the driver circuit is to be in the second state;
• wherein a steady-state voltage of the first output of the driver circuit when the first control signal is HIGH is a voltage within the range 100 millivolts to 350 millivolts, inclusive;
• wherein a steady-state voltage of the second output of the driver circuit when the second control signal is HIGH is a voltage within the range 100 millivolts to 350 millivolts, inclusive.