Back to results
US 7,609,111 B2Granted
Negative capacitance synthesis
AssigneeIntersil Americas Inc.
InventorsPhilip V. Golden, Peter J. Mole
Life of this patent
Estimating the term…
Abstract
Provided herein are negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of an output stage. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion.
Claims21
A negative capacitance circuit, comprising:
- a first transistor (Qn1, Qp1, Mn3 or Mp3) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the first transistor connected to a first voltage rail (Vsp or Vsm);
- a second transistor (Qn2, Qp2, Mn4 or Mp4) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the second transistor connected to the control terminal (base or gate) of the first transistor, and the control terminal (base or gate) of the second transistor receiving a bias voltage;
- a first bias current source (Ibias) connected between the second current path terminal (emitter or source) of the first transistor and a second voltage rail (Vsm or Vsp);
- a second bias current source (Ibias) connected between the second current path terminal (emitter or source) of the second transistor and the second voltage rail (Vsm or Vsp);
- a capacitor (C1) connected between the second current path terminal (emitter or source) of the first transistor and the second current path terminal (emitter or source) of the second transistor;
- and
- a resistor (Rc) including a first resistor terminal and second resistor terminal, the first resistor terminal connected to the control terminal (base or gate) of the first transistor and to the first current path terminal (collector or drain) of the second transistor, and the second resistor terminal forming the input node of the negative capacitance circuit.
4 more elements
A negative capacitance circuit, comprising:
- a first transistor (Qn1, Qp1, Mn3 or Mp3) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the first transistor connected to a first voltage rail (Vsp or Vsm);
- a second transistor (Qn2, Qp2, Mn4 or Mp4) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the second transistor connected to the control terminal (base or gate) of the first transistor, and the control terminal (base or gate) of the second transistor receiving a bias voltage;
- a first bias current source (Ibias) connected between the second current path terminal (emitter or source) of the first transistor and a second voltage rail (Vsm or Vsp);
- a second bias current source (Ibias) connected between the second current path terminal (emitter or source) of the second transistor and the second voltage rail (Vsm or Vsp);
- a capacitor (C1) connected between the second current path terminal (emitter or source) of the first transistor and the second current path terminal (emitter or source) of the second transistor;
- a resistor Rc) including a first resistor terminal and second resistor terminal, the first resistor terminal connected to the control terminal (base or gate) of the first transistor and to the first current path terminal (collector or drain) of the second transistor, and the second resistor terminal forming the input node of the negative capacitance circuit;
- and
- a voltage offset device (Voffset);
- wherein the capacitor (C1) includes a first capacitor terminal and a second capacitor terminal;
- wherein the voltage offset device (Voffset) is connected between the second current path terminal of the first transistor and the first capacitor terminal;
- wherein the second capacitor terminal is connected to the second current path terminal of the second transistor;
- and
- wherein the bias voltage provided to the control terminal of the second transistor is equal to or substantially equal to the offset voltage, provided by the voltage offset device (Voffset), plus a voltage drop across the resistor (Rc).
10 more elements
A negative capacitance circuit, comprising:
- a first transistor (Qn1, Qp1, Mn3 or Mp3) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the first transistor connected to a first voltage rail (Vsp or Vsm);
- a second transistor (Qn2, Qp2, Mn4 or Mp4) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the second transistor connected to the control terminal (base or gate) of the first transistor, and the control terminal (base or gate) of the second transistor receiving a bias voltage;
- a first bias current source (Ibias) connected between the second current path terminal (emitter or source) of the first transistor and a second voltage rail (Vsm or Vsp);
- a second bias current source (Ibias) connected between the second current path terminal (emitter or source) of the second transistor and the second voltage rail (Vsm or Vsp);
- a capacitor (C1) connected between the second current path terminal (emitter or source) of the first transistor and the second current path terminal (emitter or source) of the second transistor;
- a resistor (Rc) including a first resistor terminal and second resistor terminal, the first resistor terminal connected to the control terminal (base or gate) of the first transistor and to the first current path terminal (collector or drain) of the second transistor, and the second resistor terminal forming the input node of the negative capacitance circuit;
- and
- a voltage offset device (Voffset);
- wherein the voltage offset device (Voffset) is connected between the control terminal of the first transistor and the first current path terminal of the second transistor;
- and
- wherein the bias voltage provided to the control terminal of the second transistor is equal to or substantially equal to the offset voltage, provided by the voltage offset device (Voffset), plus a voltage drop across the resistor (Rc).
8 more elements
A negative capacitance circuit, comprising:
- at least two transistors;
- a resistor Rc;
- and
- a capacitor C1;
- wherein the negative capacitance circuit has an input impedance
- Zin
- ≈
- -
- 1
- jω
-
-
- C
- 1
- -
- 2
- gm
- +
- R
- C
- ,
- where
- gm is the transconductance of the transistors of the negative capacitance circuit, and
- R
- C
- ≈
-
- 2
- gm
-
- .
28 more elements
Dependencies are inferred from the claim text.