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US 7,609,104 B2Granted
Spread spectrum clock generator
AssigneeToshiba America Electronic Components, Inc.
InventorMasao Kaizuka
Life of this patent
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Abstract
A digitally controlled delay line generates a clock signal. The clock signal can be modulates as a spread spectrum clock signal. In an example embodiment, the programmable delay line has an input for receiving a signal, an output that delays outputting the input signal by a time period programmed into a delay value input. A feedback loop comprising an inverter is coupled between the input and the output of the programmable delay line.
Claims17
An apparatus, comprising:
- a programmable delay line, the programmable delay line comprising a signal input, a signal output and a delay value input;
- an inverter coupled between the signal input and the signal output;
- and
- a delay select circuit, the delay select circuit comprises a first input having a first input data length, a second input having a second input data length and an output having a data length less than the combined data length of the first input and the second input;
- wherein a signal received at the signal input is delayed by a time period based on a value received at the delay value input before appearing at the signal output
- wherein the output of the delay select circuit is coupled to the delay value input of the programmable delay line;
- and
- wherein the programmable delay line is responsive to delay the signal received at the signal input by an amount of time specified by the delay select circuit.
5 more elements
An apparatus, comprising:
- application specific logic, the application specific logic comprises a programmable delay line, the programmable delay line comprising a signal input, a signal output and a delay value input, and an inverter coupled between the signal input and the signal output, wherein a signal received at the signal input is delayed by a time period based on a value received at the delay value input before appearing at the signal output;
- a reference clock signal coupled to the application specific logic;
- a double data rate synchronous dynamic random access memory coupled to the application specific logic;
- a flash memory coupled to the application specific logic;
- and
- a complementary-symmetry metal-oxide semiconductor sensor coupled to the application specific logic.
3 more elements
An apparatus comprising:
- programmable delay means, the programmable delay means comprising an input means and an output means and is responsive to receiving a signal at the input means to delay the signal a predetermined amount of time before outputting the signal at the output means;
- inverting means coupled between the input means and the output means;
- and
- delay select means, the delay select means comprises a first input having a first input data length, a second input having a second input data length and an output having a data length less than the combined data length of the first input and the second input;
- wherein the output of the delay select means is coupled to a delay value input of the programmable delay means;
- and
- wherein the programmable delay means is responsive to delay the signal received at the input means by an amount of time specified by the delay select means.
4 more elements
A method, comprising
- selecting a delay value;
- receiving a signal at an input of a delay circuit;
- outputting the signal to an output of the delay circuit after a time period corresponding to the delay value has elapsed;
- and
- inverting the signal from the output of the delay circuit and sending the inverted signal to the input of the delay circuit;
- and
- adjusting the delay value wherein during a predefined period a first predetermined number of clock signals having a first period are generated and a second predetermined number of clock signals having a second period are generated.
4 more elements
A method, comprising
- selecting a delay value;
- receiving a signal at an input of a delay circuit;
- outputting the signal to an output of the delay circuit after a time period corresponding to the delay value has elapsed;
- and
- inverting the signal from the output of the delay circuit and sending the inverted signal to the input of the delay circuit;
- and
- adjusting the delay value for generating a clock pattern such that a spread spectrum clock is generated.
4 more elements
Dependencies are inferred from the claim text.