Pattern-dependent phase detector for clock recovery

A method of providing phase correction signals to a clock signal generator, comprising the steps of:

• (i) obtaining a received signal sample sequence;
• (ii) determining a relative phase between a clock signal and a received data signal in response to the received signal sample sequence;
• (iii) determining whether a data transition has occurred in response to the received signal sample sequence;
• and,
• (iv) determining whether the received signal sample sequence is equal to a predetermined signal sample sequence, and if so, generating a pattern dependent phase correction signal in response to the determined relative phase, wherein the predetermined signal sample sequence is a transition from 1 to 0.

A method of providing phase correction signals to a clock signal generator

• comprising the steps:
• (i) obtaining a received signal sample sequence, wherein the signal sample sequence contains at least some multi-bit samples;
• (ii) determining a relative phase between a clock signal and a received data signal in response to the received signal sample sequence;
• (iii) determining whether a predetermined data transition has occurred in response to the multi-bit samples, wherein the predetermined data transition is a transition from one to zero, and, if so,
• (iv) generating a pattern dependent phase correction signal in response to the determined relative phase.