Frequency synthesizer and method for constructing the same

A frequency synthesizer having a reference frequency as an input signal and an output frequency as an output signal, the frequency synthesizer comprising:

• an N1 counter for dividing said reference frequency by a number of N1 and delivering an enable signal;
• an N2 counter for receiving said enable signal from said N1 counter, dividing said output frequency by a number of N2 when said enable signal is active, and delivering an output data;
• a processor for receiving said output data of said N2 counter and delivering an output data;
• a memory for receiving said output data of said processor and delivering an output data;
• a digital to analog converter (DAC) for receiving and converting said output data of said memory and delivering an analog output signal;
• and
• a voltage control oscillator (VCO) for receiving said output signal of said DAC and delivering said output frequency;
• wherein said DAC comprises a DAC register for storing said output data of said memory for said DAC to generate said output signal.

A method for constructing a frequency synthesizer having an N1 counter, an N2 counter, a processor, a DAC, and a VCO, the method comprising the steps of:

• inputting a reference frequency to said N1 counter as a time base for said frequency synthesizer;
• driving said N1 counter to generate an enable signal by dividing said reference frequency by a number of N1;
• driving said N2 counter to generate an output data coupled to said processor by dividing an output frequency of said VCO by a number of N2 when said enable signal is active;
• driving said processor to generate an output data coupled to a DAC register of said DAC;
• driving said DAC to generate an analog output signal coupled to a VCO by said output data of said DAC register;
• and
• driving said VCO to generate said output frequency coupled to said N2 counter.

A method for constructing a frequency synthesizer having an N1 counter, an N2 counter, a processor, a memory, a DAC, and a VCO, the method comprising the steps of:

• inputting a reference frequency to said N1 counter as a time base for said frequency synthesizer;
• driving said N1 counter to generate an enable signal by dividing said reference frequency by a number of N1;
• driving said N2 counter to generate an output data coupled to said processor by dividing an output frequency by a number of N2 when said enable signal is active;
• driving said processor to generate an output data coupled to said memory as a memory address;
• driving said memory to generate an output data coupled to a DAC register of said DAC;
• driving said DAC to generate an analog output signal coupled to a VCO by said output data of said DAC register;
• and
• driving said VCO to generate said output frequency coupled to said N2 counter.