Automatic phase-detection circuit for clocks with known ratios
AssigneeSun Microsystems, Inc.
InventorsThomas Wicki, Bharat Daga
Life of this patent
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Abstract
An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared.
Claims22
An automatic phase detection circuit for clocks, comprising:
- a sequential state element having a data input, a first clock input and a data output;
- a first clock operably coupled to the data input;
- a second clock operably coupled to the first clock input;
- a serial input, parallel output shift register having a second clock input operably coupled to the second clock and the serial input operably coupled to the data output;
- a signature register configured to store a repetitive portion of an output sequence of the data output;
- a comparator operably coupled to the parallel output of the shift register and operably coupled to the signature register, the comparator configured to compare a content of the signature register and a content of the shift register;
- and
- wherein the comparator generates a pulse when the content of the signature register and the content of the shift register match.
A method of performing automatic phase detection for clocks with a certain frequency ratio, the method comprising:
- receiving a first clock signal and a second clock signal;
- identifying a repetitive sequence that occurs when an active edge of the first clock signal is used to sample a logic state of the second clock signal;
- sampling the second clock signal on each active edge of the first clock signal to obtain a sample sequence;
- and
- generating a sync pulse when the sample sequence matches the repetitive sequence.
A programmable clock module having a first clock input and a second clock input, comprising:
- a sequential state element having a data input operably coupled to the first clock input, a data output and a clock input operably coupled to the second clock input;
- a serial input port, parallel output port n-bit shift register having a clock input port, the clock input port operably coupled to the second clock input and the serial input port operably coupled to the data output;
- an n-bit comparator operably coupled to the shift register and configured to compare a content of the shift register with a pre-defined signature;
- an n-bit mask register operably coupled to the comparator and configured to mask a portion of the comparison;
- and
- wherein the comparator generates a pulse when the content of the shift register matches the pre-defined signature.
Dependencies are inferred from the claim text.