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US 7,609,088 B2Granted
Programmable logic array
AssigneeSamsung Electronics Co., Ltd.
InventorDong-Gyu Lee
Life of this patent
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Abstract
A programmable logic array (PLA) which may include an AND-plane receiving first input signals and generating logic product signals based on the first input signals, and an OR-plane receiving the logic product signals and a second input signal and generating a logic sum signal based on the logic product signals.
Claims16
A programmable logic array comprising:
- an AND-plane receiving first input signals and generating logic product signals based on the first input signals;
- and
- an OR-plane receiving the logic product signals and a delayed second input signal inputted later than the first input signals and generating a logic sum signal based on the logic product signals.
An OR-plane comprising:
- a receiving circuit receiving logic product signals and an input signal;
- and
- a generating circuit generating a logic sum signal based on the logic product signals, wherein the generating circuit includes,
- a first logic sum generating circuit generating a first logic sum signal based on a first subset of the logic product signals;
- a second logic sum generating circuit generating a second logic sum signal based on a second subset of the logic product signals;
- and
- a logic sum generating circuit generating the logic sum signal by varying the first logic sum signal according to a logic state of the input signal and the second logic sum signal.
4 more elements
A method of performing a logic function comprising:
- receiving input signals including first input signals and a delayed second input signal inputted later than the first input signals;
- generating logic product signals based on the first input signals;
- generating a logic sum signal based on the logic product signals;
- and
- varying the logic sum signal according to a logic state of the delayed second input signal.
2 more elements
A programmable logic array comprising:
- an AND-plane receiving first input signals and generating logic product signals based on the first input signals;
- and
- an OR-plane receiving the logic product signals and a delayed second input signal and generating a logic sum signal based on the logic product signals, wherein the OR-plane includes,
- a logic circuit generating a first logic sum signal based on a first subset of the logic product signals, generating a second logic sum signal based on a second subset of the logic product signals, and generating the logic sum signal by varying the first logic sum signal according to a logic state of the delayed second input signal and the second logic sum signal.
1 more element
A method of performing a logic function comprising:
- receiving input signals including first input signals and a delayed second input signal;
- generating logic product signals based on the first input signals;
- generating a logic sum signal based on the logic product signals;
- and
- varying the logic sum signal according to a logic state of the delayed second input signal, wherein generating a logic sum signal includes,
- generating a first logic sum signal based on a first subset of the logic product signals;
- and
- generating a second logic sum signal based on a second subset of the logic product signals;
- and
- wherein the varying the logic sum signal step includes,
- varying the first logic sum signal according to a logic state of the delayed second input signal and the second logic sum signal.
8 more elements
Dependencies are inferred from the claim text.