Output level stabilization circuit and CML circuit using the same
AssigneeNEC Corporation
InventorYusuke Matsushima
Life of this patent
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Abstract
An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit.
Claims4
An output level stabilization circuit for a CML circuit, the output level stabilization circuit comprising:
- a replica circuit comprising of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor;
- a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit;
- a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit;
- a noise detection unit which detects a noise in the comparison result;
- and
- a control unit which variably controls the impedance of the variable impedance circuit in response to the noise detection.
Dependencies are inferred from the claim text.