Deterministic generation of an integrated circuit identification number
AssigneeSTMicroelectronics S.r.l.
InventorFabrice Marinet
Life of this patent
Estimating the term…
Abstract
The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number.
Claims21
An integrated circuit chip comprising,
- on at least one side, at least two conductive sections having two end terminals connected to the inside of the chip to generate an identification number thereof, the generation of the identification number dependent on the position of a cutting line with respect to the corresponding edge of the chip;
- and
- a read circuit coupled to each conductive section and operable to determine the state of each section.
An integrated circuit chip, comprising:
- a first edge;
- and
- first conductive paths disposed on the first edge, each one having a closed or open state, wherein a combination of the states identifies the chip;
- and
- a reading circuit coupled to each conductive path and operable to read the states of the first conductive paths.
An integrated circuit chip, comprising:
- a first edge;
- first conductive paths disposed on the first edge, each one having a closed or open state, wherein a combination of the states identifies the chip a second edge;
- second conductive paths disposed on the second edge, each one having a closed or open state;
- and
- a read circuit coupled to each of the first conductive paths and each of the second conductive paths and operable to determine the state of each path.
An integrated circuit, comprising:
- an integrated circuit chip including,
- a first edge;
- first conductive paths disposed on the first edge, each one having a closed or open state, wherein a combination of the states identifies the chip;
- a read circuit coupled to each of the first conductive paths and operable to determine the state of each path;
- and
- a memory having an identification stored therein, the identification generated from the combination of states of the first conductive paths.
A system, comprising:
- a first integrated circuit including,
- a first edge;
- and
- first conductive paths disposed on the first edge, each one having a closed or open state, wherein a combination of the states identifies the chip;
- and
- a reading circuit coupled to each conductive path and operable to read the states of the first conductive paths.
An integrated circuit, comprising:
- a circuit portion having circuit nodes;
- a first edge disposed adjacent to the circuit portion;
- conductive paths disposed on the first edge, each conductive path coupled between a respective pair of the circuit nodes such that a conductive path has a closed state if the path electrically couples together the respective pair of nodes and has an open state if the path does not electrically couple together the respective pair of nodes, at least one of the conductive paths having a closed state;
- and
- a reading circuit coupled to each conductive path operable to store an identifier based on the states of the conductive paths.
Dependencies are inferred from the claim text.