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US 7,608,927 B2Granted
Localized biasing for silicon on insulator structures
AssigneeMicron Technology, Inc.
InventorsFernando Gonzalez, John K. Zahurak
Life of this patent
Estimating the term…
Abstract
A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
Claims68
A silicon-on-insulator semiconductor device, comprising:
- a substrate configured to include a substrate potential;
- an insulator in contact with the substrate;
- a patterned conductor layer within the insulator and not extending vertically above the insulator and electrically insulated from the substrate, the patterned conductor layer includes a voltage biased, local portion;
- a silicon layer formed on and in contact with the insulator and the patterned conductor layer, wherein the voltage biased, local portion is configured to adjust a bias potential of the silicon layer independent of the substrate potential;
- at least one integrated circuit device formed in the silicon layer;
- and
- wherein the voltage biased, local portion has a horizontal dimension greater than a horizontal dimension of the integrated circuit device.
4 more elements
A silicon-on-insulator semiconductor device, comprising:
- a substrate configured to include a substrate potential;
- an insulator in contact with the substrate;
- a patterned conductor within the insulator and defining a plurality of voltage biasing portions electrically insulated from the substrate;
- a silicon layer formed on and in contact with the insulator and the patterned conductor, wherein the plurality of voltage biasing portions are configured to provide a localized bias voltage to a different region of the silicon layer independent of the substrate potential;
- and
- at least one integrated circuit device formed in the silicon layer;
- wherein the patterned conductor provides the localized bias voltage through one of the plurality of voltage biasing portions to the integrated circuit device, and wherein the one voltage biasing portion has a horizontal dimension greater than a horizontal dimension of the integrated circuit device.
4 more elements
A silicon-on-insulator semiconductor device, comprising:
- a substrate configured to include a substrate potential;
- an insulator in contact with the substrate;
- a recess formed in the insulator, wherein the recess has a depth of about 500 angstroms;
- a localized biasing conductor in the recess that is electrically isolated from the substrate;
- a silicon layer formed on and in contact with the insulator and the conductor;
- at least one integrated circuit device formed in the silicon layer;
- and
- the conductor including a first part being in contact with a first portion of the silicon layer to provide a localized bias to the first portion of the silicon layer that is different than a bias to a second portion of the silicon layer, the first part having a horizontal dimension greater than a horizontal dimension of the first portion of the silicon layer, wherein the first portion and the second portion are configured to receive the different localized bias voltages independent of the substrate potential.
5 more elements
A silicon-on-insulator semiconductor device, comprising:
- a substrate configured to include a substrate potential;
- an insulator in contact with the substrate;
- a recess in the insulator;
- a localized biasing conductor in the recess that is electrically isolated from the substrate;
- a silicon layer formed on and in contact with the insulator and the conductor;
- at least one integrated circuit device formed in the silicon layer;
- wherein the localized biasing conductor includes a localized biased portion configured to provide a localized bias voltage to the integrated circuit device to adjust a bias potential of the integrated circuit device independent of the substrate potential;
- wherein the localized biased portion has a horizontal dimension greater than a horizontal dimension of the integrated circuit device;
- and
- wherein the conductor has a top surface substantially planar with the top surface of the insulator, and the silicon layer being on the top surfaces of both the conductor layer and the insulator layer.
7 more elements
A silicon-on-insulator semiconductor device, comprising:
- a substrate;
- an insulator in contact with the substrate;
- a recess in the insulator;
- a first localized biasing conductor in the recess;
- a second localized biasing conductor in the insulator, the second localized biasing conductor providing a bias voltage different than the first localized biasing conductor, wherein the first localized biasing conductor and the second localized biasing conductor are electrically insulated from the substrate;
- a silicon layer formed on and in contact with the insulator and the conductor;
- and
- a transistor formed in the silicon layer;
- wherein the first localized biasing conductor is adapted to provide a bias voltage to the transistor.
6 more elements
A silicon-on-insulator semiconductor device, comprising:
- a substrate;
- an insulator in contact with the substrate;
- a first patterned conductor within the insulator and electrically insulated from the substrate;
- a first voltage source connected to the first patterned conductor;
- a second patterned conductor within the insulator and electrically insulated from the substrate;
- a second voltage source connected to the second patterned conductor;
- a silicon layer formed on and in contact with the insulator, the first patterned conductor and the second patterned conductor;
- at least one first integrated circuit device formed in the silicon layer;
- wherein the first patterned conductor is adapted to provide a first bias voltage to the first integrated circuit;
- at least second integrated circuit device formed in the silicon layer;
- wherein the second patterned conductor is adapted to provide a second bias voltage to the second integrated circuit.
8 more elements
An integrated circuit memory device, comprising:
- a silicon-on-insulator structure;
- an access circuit;
- a memory array operably connected to the access circuit;
- wherein at least one of the access circuit and the memory cell array is in the silicon-on-insulator structure;
- and
- wherein the silicon on insulator structure includes:
- a substrate configured to include a substrate potential;
- an insulative layer in contact with the substrate;
- a conductor within the insulative layer, the conductor including a local portion to provide a bias signal to the at least one of the access circuit and the memory cell array, the local portion adapted to provide the bias signal to the access circuit and the memory cell array independent of the substrate potential;
- a silicon layer on and in contact with the insulative layer and the conductor;
- and
- wherein the local portion has a horizontal dimension greater than a horizontal dimension of an integrated circuit device of the at least one of the access circuit and the memory cell array.
9 more elements
A silicon-on-insulator integrated circuit device, comprising:
- a substrate;
- an insulator layer in contact with the substrate;
- a recess in the insulator layer;
- a patterned biasing conductor layer in the recess and electrically insulated from the substrate by the insulator layer;
- a silicon layer formed on and in contact with both the insulator layer and at least a portion of the patterned biasing conductor layer;
- a body region formed in the silicon layer over the portion of the conductor layer;
- a first source/drain region formed in the silicon layer adjacent the body region;
- a second source/drain region formed in the silicon layer adjacent the body region and remote the first source/drain region;
- a gate formed on the body region intermediate the first source/drain region and the second source/drain region;
- and
- wherein the patterned biasing conductor layer is adapted to provide a first bias voltage to the body region and a second bias voltage to a further portion of the silicon layer.
8 more elements
A silicon-on-insulator semiconductor device, comprising:
- a substrate;
- an insulator in contact with the substrate;
- a patterned, voltage-biasing conductor layer within the insulator and electrically insulated from the substrate by the insulator layer;
- a silicon layer formed on and in contact with the insulator and the conductor layer;
- and
- the conductor remaining below the silicon layer and being adapted to provide a plurality of bias voltages.
3 more elements
A silicon-on-insulator semiconductor device, comprising:
- a substrate configured to include a substrate potential;
- an insulator in contact with the substrate;
- a conductor layer within the insulator, wherein the conductor layer includes a voltage biased, local portion;
- a silicon layer formed on and in contact with the insulator and the conductor layer, wherein the silicon layer includes at least one integrated circuit device formed in the silicon layer and is biased by the voltage biased, local portion of the conductor layer, and wherein the voltage biased, local portion is configured to bias the integrated circuit independent of the substrate potential;
- a discharge circuit connected to the conductor layer;
- and
- wherein the voltage biased, local portion has a horizontal dimension greater than a horizontal dimension of the biased, integrated circuit device.
4 more elements
Dependencies are inferred from the claim text.