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US 7,608,919 B1Granted
Interconnect packaging systems
AssigneeUniversity of Notre Dame du Lac
InventorsGary H. Bernstein, Patrick Fay, Wolfgang Porod, Qing Liu
Life of this patent
Estimating the term…
Abstract
The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.
Claims25
A microchip packaging system comprising:
- a first microchip having a convex shape comprising three or more edge surfaces, a plurality of said edge surfaces having one or more interconnect modules disposed thereon;
- and
- at least a second microchip having a convex shape comprising three or more edge surfaces, a plurality of said edge surfaces having one or more interconnect nodules disposed thereon,
- wherein a first edge surface of said second microchip is positioned contiguous to a first edge surface of said first microchip, and wherein at least one of said one or more interconnect nodules disposed on said first edge surface of said first microchip is configured to be in physical contact with at least one of said one or more interconnect nodules disposed on said first edge surface of second microchip so as to provide a direct electrical connection between said at least one edge surfaces of said first and second microchips.
1 more element
A quilt packaging system comprising:
- a first electronic device having a convex shape comprising three or more edge surfaces, a plurality of said edge surfaces having one or more interconnect modules disposed thereon;
- and
- at least a second electronic device having a convex shape comprising three or more edge surfaces, a plurality of said edge surfaces having one or more interconnect nodules disposed thereon,
- wherein a first edge surface of said second electronic device is positioned contiguous to a first edge surface of said first electronic device, and wherein at least one of said one or more interconnect nodules disposed on said first edge surface of said first electronic device is configured to be in physical contact with at least one of said one or more interconnect nodules disposed on said first edge surface of second electronic device so as to provide a direct electrical connection between said at least one edge surfaces of said first and second electronic devices.
1 more element
Dependencies are inferred from the claim text.