Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress

A semiconductor device, comprising:

• a first device region including a plurality of first P-channel transistors and first N-channel transistors, said first P-channel transistors and said first N-channel transistors forming a first functional block;
• a second device region including a plurality of second P-channel transistors and second N-channel transistors, said second P-channel transistors and said second N-channel transistors forming a second functional block;
• a first dielectric contact etch stop layer formed in said first device region, said first dielectric contact etch stop layer comprising a plurality of first portions having a first intrinsic stress value and a plurality of second portions having a second intrinsic stress value other than said first intrinsic stress value, said first portions of said first dielectric layer being formed above said first P-channel transistors and said second portions of said first dielectric layer being formed above said first N-channel transistors;
• and
• a second dielectric contact etch stop layer formed in said second device region, said second dielectric contact etch stop layer comprising a plurality of first portions of said second dielectric layer having said first intrinsic stress value and a plurality of second portions of said second dielectric layer having a third intrinsic stress value other than said first and second intrinsic stress values, said first portions of said second dielectric layer being formed above said second P-channel transistors and said second portions of said second dielectric being formed above said second N-channel transistors.