One transistor DRAM cell structure

A one-transistor dynamic random access memory (DRAM) cell comprising:

• a transistor having a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region, wherein the first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region and an ohmic contact in series with the n-p diode junction,
• wherein the first source/drain region includes a first silicide layer extending under the gate,
• the second source/drain region includes a second silicide layer extending under the gate and a source/drain extension region extending under the gate,
• wherein each of the first and second source/drain regions include a deep source/drain region and wherein the first source/drain region is devoid of a source/drain extension region, and
• wherein:
• when the transistor is characterized as an N-channel transistor, the majority carriers are removed from the body region via the Schottky diode junction during a write operation of the DRAM cell in response to a potential at the first source/drain region being lower than a potential at the second source/drain region, and
• when the transistor is characterized as a P-channel transistor, the majority carriers are removed from the body region via the Schottky diode junction during a write operation of the DRAM cell in response to a potential at the first source/drain region being higher than a potential at the second source/drain region.