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US 7,608,886 B2Granted
Systems and methods for a high density, compact memory array
AssigneeMacronix International Co., Ltd.
InventorsTzu-Hsuan Hsu, Ming-Hsiu Lee, Chao-I Wu, Ming-Chang Kuo
Life of this patent
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Abstract
A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
Claims31
A memory array, comprising:
- a first vertical memory cell comprising a first plurality of transistor structures;
- a second vertical memory cell comprising a second plurality of transistor structures;
- a joint drain region between the first and second memory cells;
- a common source region between the first and the second memory cells;
- and
- a joint body region between the first memory cell and the second memory cell,
- wherein each of the first plurality of transistor structures share a first common conductive gate region wholly disposed above the common source region.
4 more elements
A memory array, comprising:
- a first vertical memory cell comprising a first plurality of transistor structures;
- a second vertical memory cell comprising a second plurality of transistor structures;
- a joint drain region between the first and second memory cells;
- a joint body region between the first memory cell and the second memory cell;
- a joint source region between the first memory cell and the second memory cell;
- and
- a word line that runs substantially parallel with the joint body region,
- wherein each of the first plurality of transistor structures share a first common conductive gate region disposed wholly above the joint source region.
5 more elements
Dependencies are inferred from the claim text.