Split-gate non-volatile memory
AssigneeMacronix International Co., Ltd.
InventorsHsiang-Lan Lung, Rui-Chen Liu
Life of this patent
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Abstract
A split-gate non-volatile memory cell is described, including a substrate, a charge-trapping layer on the substrate, a split gate on the charge-trapping layer, and a source/drain in the substrate beside the split gate. The split gate includes at least one split region directly over the charge-trapping layer, and the charge-trapping layer around the split region serves as a coding region. A NAND non-volatile memory array is also described including the above-mentioned split-gate non-volatile memory cells that are arranged in a NAND-type configuration.
Claims12
A split-gate non-volatile memory cell, comprising:
- a substrate;
- a charge-trapping layer on the substrate;
- a split gate as a whole located over the charge-trapping layer, being a part of one word line of a non-volatile memory array including the split-gate non-volatile memory cell;
- and
- a source/drain in the substrate beside the split gate,
- wherein the split gate includes at least two neighboring conductive pieces that are shorted with each other and have two opposite edge portions together causing, in operation of the memory cell, a locally stronger electric field such that only one coding region is defined, by the two neighboring conductive pieces, in the charge-trapping layer around the two opposite edge portions.
An operating method of a split-gate non-volatile memory cell, wherein
- the split-gate non-volatile memory cell comprises:
- a substrate;
- a charge-trapping layer on the substrate;
- a split gate as a whole located over the charge-trapping layer, being a part of one word line of a non-volatile memory array including the split-gate non-volatile memory cell;
- and
- a source/drain in the substrate beside the split gate,
- wherein the split gate includes at least two neighboring conductive pieces that are shorted with each other and have two opposite edge portions together causing, in operation of the memory cell, a locally stronger electric field such that only one coding region is defined, by the two neighboring conductive pieces, in the charge-trapping layer around the two opposite edge portions;
- and the operating method comprises:
- in a programming operation:
- applying 0V to the substrate and the source/drain;
- and
- applying a first negative voltage to the split gate, the first negative voltage being sufficiently high for injecting electrons into the coding region;
- and
- in an erasing operation:
- applying 0V to the split gate, wherein each conductive piece is at an electric state of 0 V;
- floating the source/drain;
- and
- applying a second negative voltage to the substrate, the second negative voltage being sufficiently high for ejecting electrons from the coding region.
Dependencies are inferred from the claim text.