Merged MOS-bipolar capacitor memory cell

A memory array, comprising:

• a number of memory cells formed on a substrate, wherein each memory cell includes:
• a semiconductor pillar, including:
• a first conductivity region with n-type doping on a substrate;
• a second conductivity region with p-type doping on the first conductivity region;
• a third conductivity region with n-type doping on the second conductivity region;
• and
• a fourth conductivity region with p-type doping on the third conductivity region;
• a gate adjacent to and separated from the third conductivity region on a first side of the semiconductor pillar;
• and
• a body capacitor, including the third conductivity region and a capacitor plate adjacent to and separated from the third conductivity region on a second side of the semiconductor pillar;
• and
• wherein the memory cell has an area of 4F2, where F is a minimum feature size.

A memory array, comprising:

• a number of memory cells formed on a substrate, wherein each memory cell includes:
• a semiconductor pillar, including:
• a first conductivity region on a substrate;
• a second conductivity region on the first conductivity region;
• a third conductivity region on the second conductivity region;
• and
• a fourth conductivity region on the third conductivity region;
• a gate adjacent to and separated from the third conductivity region on a first side of the semiconductor pillar;
• and
• a body capacitor, including the third conductivity region and a capacitor plate adjacent to and separated from the third conductivity region on a second side of the semiconductor pillar;
• and
• wherein the first conductivity region is adapted to function as an emitter of a bi-polar transistor, the second conductivity region is adapted to function as a base region for a bi-polar transistor, and the third conductivity region is adapted to function as a collector region of a bi-polar transistor and as a body region of a MOS transistor.