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US 7,608,873 B2Granted
Buried-gated photodiode device and method for configuring and operating same
AssigneeAptina Imaging Corporation
InventorJeffery S. Beck
Life of this patent
Estimating the term…
Abstract
A 3-T buried-gated photodiode device that is suitable for use in a windowed array. The 3-T buried-gated photodiode device is configured such that the floating diffusion (FD) node of the device is held low when the device is not being specifically addressed, which ensures that the device cannot drive the corresponding pixel output line unless it is specifically addressed.
Claims13
A photodiode device comprising:
- a source follower (SF) transistor having first and second terminals and a gate terminal, the first terminal being electrically coupled to a power supply, the second terminal being electrically coupled to a pixel output line, the gate terminal being electrically coupled to a floating diffusion (FD) node;
- a reset transistor having a first and second terminals and a gate terminal, the first terminal of the reset transistor being electrically coupled to the FD node, the second terminal of the reset transistor being electrically coupled to a select (SEL) terminal that receives a SEL timing signal, the gate terminal of the reset transistor being directly connected to the pixel output line;
- a transfer (TX) transistor having first and second terminals and a gate terminal, the gate terminal of the TX transistor being electrically coupled to a TX terminal that receives a TX timing signal, the first terminal of the TX transistor being electrically coupled to the FD node;
- and
- a photodiode having a cathode terminal and an anode terminal, the cathode terminal being electrically coupled to the second terminal of the TX transistor, the anode terminal being electrically coupled to ground.
2 more elements
An integrated circuit (IC) comprising an array of photodiode devices, each photodiode device comprising:
- a source follower (SF) transistor having first and second terminals and a gate terminal, the first terminal being electrically coupled to a power supply, the second terminal being electrically coupled to a pixel output line, the gate terminal being electrically coupled to a floating diffusion (FD) node;
- a reset transistor having a first and second terminals and a gate terminal, the first terminal of the reset transistor being electrically coupled to the FD node, the second terminal of the reset transistor being electrically coupled to a select (SEL) terminal that receives a SEL timing signal, the gate terminal of the reset transistor being directly connected to the pixel output line;
- a transfer (TX) transistor having first and second terminals and a gate terminal, the gate terminal of the TX transistor being electrically coupled to a TX terminal that receives a TX timing signal, the first terminal of the TX transistor being electrically coupled to the FD node;
- and
- a photodiode having a cathode terminal and an anode terminal, the cathode terminal being electrically coupled to the second terminal of the TX transistor, the anode terminal being electrically coupled to ground.
2 more elements
An integrated circuit (IC) comprising an array of photodiode devices, each photodiode device comprising:
- a source follower (SF) transistor having first and second terminals and a gate terminal, the first terminal being electrically coupled to a power supply, the second terminal being electrically coupled to a pixel output line, the gate terminal being electrically coupled to a floating diffusion (FD) node;
- a reset transistor having a first and second terminals and a gate terminal, the first terminal of the reset transistor being electrically coupled to the FD node, the second terminal of the reset transistor being electrically coupled to a select (SEL) terminal that receives a SEL timing signal, the gate terminal of the reset transistor being directly connected to the pixel output line;
- a first transfer (TX1) transistor having first and second terminals and a gate terminal, the gate terminal of the TX1 transistor being electrically coupled to a TX1 terminal that receives a TX1 timing signal, the first terminal of the TX1 transistor being electrically coupled to the FD node;
- a photodiode having a cathode terminal and an anode terminal, the cathode terminal being electrically coupled to the second terminal of the TX1 transistor, the anode terminal being electrically coupled to ground;
- a second transfer (TX2) transistor having first and second terminals and a gate terminal, the gate terminal of the TX2 transistor being electrically coupled to a TX2 terminal that receives a TX2 timing signal, the first terminal of the TX2 transistor being electrically coupled to the FD node;
- and
- a second photodiode having a cathode terminal and an anode terminal, the cathode terminal being electrically coupled to the second terminal of the TX2 transistor, the anode terminal being electrically coupled to ground, and wherein the TX1 and TX2 timing signals are time division multiplexed.
4 more elements
Dependencies are inferred from the claim text.