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US 7,608,788 B2Granted
Plating buss and a method of use thereof
AssigneeMicron Technology, Inc.
InventorMark S. Johnson
Life of this patent
Estimating the term…
Abstract
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing short circuit problems due to indexing errors caused by occasional manufacturing and equipment alignment problems. The serpentine plating buss design therefore increases board yield.
Claims17
A substrate panel comprising:
- a plurality of printed circuit boards suitable for singulation using a saw blade having a width defining a first process window, each printed circuit board having a plurality of conductive traces provided on a planar surface of the substrate, wherein said plurality of conductive traces on one of said plurality of printed circuit boards is offset from said plurality of conductive traces on an adjacent one of said plurality of printed circuit boards;
- and
- a serpentine plating buss provided on said planar surface between adjacent ones of said plurality of printed circuit boards and interconnecting said plurality of offset conductive traces, and wherein said serpentine plating buss comprises a plurality of lateral segments positioned perpendicularly across said first process window, and a plurality of nonparallel side segments, wherein said serpentine plating buss extends laterally in a full pattern a distance greater than the width of the saw blade such that said serpentine plating bus defines a second process window significantly larger than the first process window.
A substrate panel comprising:
- a plurality of printed circuit boards suitable for singulation using a saw blade having a width defining a first process window, each printed circuit board having a plurality of conductive traces provided on a planar surface of the substrate, wherein said plurality of conductive traces on one of said plurality of printed circuit boards is offset from said plurality of conductive traces on an adjacent one of said plurality of printed circuit boards;
- a serpentine plating buss provided on said planar surface between adjacent ones of said plurality of printed circuit boards and interconnecting said plurality of offset conductive traces, and wherein said serpentine plating buss comprises a plurality of lateral segments positioned perpendicularly across said first process window, and a plurality of nonparallel side segments, wherein said serpentine plating buss extends laterally in a full pattern a distance greater than the width of the saw blade such that said serpentine plating bus defines a second process window significantly larger than the first process window;
- and
- the plurality of nonparallel side segments of said serpentine plating buss are provided in a pattern selected from the group comprising accordion, saw toothed, triangular, curvilinear pattern, and combinations thereof.
1 more element
Dependencies are inferred from the claim text.