Dual gate LDMOS device fabrication methods

A method of fabricating a semiconductor device, comprising the steps of:

• providing a semiconductor substrate of a first conductivity type and first dopant concentration and having a surface;
• forming a first well of the first conductivity type and second dopant concentration in the substrate;
• forming a second well of a second, opposite, conductivity type and third dopant concentration in the substrate, wherein the second well is separated from or in contact with the first well and forms a PN junction with the first well or the substrate, which PN junction extends substantially to the surface;
• forming a third region of the second conductivity type and a fourth dopant concentration in the substrate, extending substantially to the surface and laterally separated from the first well, and adapted when biased to form a space charge region at least partly in the substrate or the first well or in a combination thereof;
• forming a first gate overlying a part of the first well or a part of the substrate between the first and second wells or both;
• forming a second gate spaced apart from the first gate and overlying at least a part of the second well;
• and
• forming an ohmic contact to the substrate within the space charge region and electrically coupled to the second gate.

A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) device, comprising the steps of:

• providing a semiconductor substrate of a first conductivity type and first concentration, having a principal surface;
• forming a source region of a second, opposite, conductivity type extending to the principal surface;
• forming a drain region of a second, opposite, conductivity type extending to the principal surface and spaced apart from the source region;
• forming a first gate above a first portion of the principal surface proximate the source region, wherein the first gate is adapted to receive a control signal;
• forming a second gate above the principal surface proximate the drain region and spaced apart from the first gate, wherein the second gate is adapted to receive a bias voltage Vg2;
• forming a further region in the substrate, wherein the further region is of the second conductivity type and further dopant concentration greater than the first concentration, and is adapted to form a space charge region in the substrate when the further region receives a voltage Vbias;
• and
• forming a body contact within the space charge region and spaced a predetermined distance from the further region, wherein the body contact is coupled to the second gate for providing voltage Vg2 to the second gate, and wherein the space charge region acts as a voltage divider so that Vg2 provided by the body contact is a predetermined fraction of Vbias applied to the further region.