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US 7,608,507 B2Granted
NAND flash memory devices and methods of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJi-Hwon Lee, Sung-Hoi Hur
Life of this patent
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Abstract
A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.
Claims18
A method of fabricating a NAND flash memory device, comprising:
- defining a plurality of active regions in a substrate;
- forming memory transistors on the active regions, the memory transistors including memory gate patterns arranged perpendicular to the plurality of active regions;
- forming lower plugs electrically connected to first regions of the plurality of active regions;
- and
- forming select transistors above the memory gate patterns, the select transistors including impurity regions, at least one impurity region of each select transistor being electrically connected to a respective first region via a lower plug.
2 more elements
Dependencies are inferred from the claim text.