Side wall active pin memory and manufacturing method

A method of forming a spacer memory cell, comprising:

• forming a first electrode, an insulating layer over the first electrode, a second electrode over the insulating layer, and a protective layer over the second electrode, with a side wall on the insulating layer using a lithographic process;
• forming a side wall spacer on the side wall, the spacer comprising a layer of a programmable resistive material in electrical communication with the first and second electrodes, the side wall spacer having a length extending from the first electrode to the second electrode along the side wall, a width generally orthogonal to the length, the spacer, the first electrode and the second electrode having respective thicknesses which are less than 40 nm, and wherein forming the side wall spacer comprises:
• depositing a layer of the programmable resistive material over the side wall and on the protective layer;
• anisotropically etching the layer of programmable resistive material to remove programmable resistive material in areas away other than the side wall;
• forming a fill material on the protective layer and surrounding the programmable resistive material on the side wall;
• planarizing the fill material to expose tops of the programmable resistive material on the sidewall and leave a remaining portion of the protective layer over the second electrode;
• forming an etch mask having a lithographic pattern to define a lithographic width;
• trimming the etch mask to provide a trimmed mask to define a pattern having a dimension less than a minimum feature size specified for the lithographic process;
• and
• selectively etching the programmable resistive material according to the pattern, to define the width of the side wall spacer, the width being less than the minimum feature size.

A memory device, including:

• a first electrode,
• an insulating member over the first electrode, the insulating member having a side wall;
• a second electrode over the insulating member;
• a programmable resistive material spacer along the side wall of the insulating member and in electrical communication with the first and second electrodes, the spacer comprising a lower portion surrounding the first electrode and an upper portion having a length extending from the lower portion to the second electrode along the side wall on the insulating layer, a width generally orthogonal to the length, and a thickness, and wherein the width and the thickness are less than 40 nm;
• and
• the spacer, the first electrode and the second electrode having respective thicknesses which are less than 40 nm, wherein the spacer, the first electrode and the second electrode have respective thicknesses which are less than a minimum lithographic feature size of a lithographic process used to form the device.

A memory device, including:

• a first electrode,
• an insulating member over the first electrode, the insulating member having a side wall;
• a second electrode over the insulating member;
• a programmable resistive material spacer along the side wall of the insulating member and in electrical communication with the first and second electrodes, the spacer comprising a lower portion surrounding the first electrode and an upper portion having a length extending from the lower portion to the second electrode along the side wall on the insulating layer, a width generally orthogonal to the length, and a thickness, and wherein the width and the thickness of the spacer are less than 40 nm, the first electrode has a thickness less than 40 nm, and the second electrode has a thickness of 10 to 30 nm.

An integrated circuit comprising:

• a semiconductor substrate;
• an array of access transistors having terminals including doped regions in the semiconductor substrate adapted to connect respective drain terminals to a reference potential;
• a plurality of word lines coupled to gate terminals of access transistors along respective rows in the array of access transistors;
• an array of programmable memory cells, the programmable memory cells in the array respectively comprising a bottom electrode, an insulating member over the bottom electrode, the insulating member having a side wall, a top electrode over the insulating member, and a programmable resistive material spacer along the side wall of the insulating member and in electrical communication with the top and bottom electrodes, the spacer having a length extending from the bottom electrode to the top electrode along the side wall on the insulating layer, a width generally orthogonal to the length, and a thickness, and wherein the width and the thickness are less than 40 nm;
• a plurality of bit lines over the array of memory cells, arranged along respective columns of memory cells in the array of programmable memory cells;
• a first plurality of contacts connecting bottom electrodes of respective memory cells with corresponding drain terminals of access transistors in the array of access transistors;
• and
• a second plurality of contacts connecting top electrodes of respective memory cells with corresponding bit lines in the plurality of bit lines.