Passivated tiered gate structure transistor and fabrication method

A method for fabricating a tiered gate structure transistor comprising a source, a drain, and a gate, the method comprising:

• forming a gate foot mask, the gate foot comprising a conductive layer on a substrate, the gate foot mask having an opening therethrough;
• forming a gate foot in the opening of the gate foot mask;
• removing the gate foot mask;
• forming a passivation layer directly contacting an uppermost surface of the source, an uppermost surface of the drain, the substrate and the gate foot;
• forming a gate head mask over the gate foot, the gate head mask having an opening therethrough exposing a portion of the passivation layer on a top portion of the gate foot;
• removing the portion of the passivation layer to expose the top portion of the gate foot;
• and
• forming a gate head on the gate foot;
• removing the gate head mask while leaving an unremoved portion of the passivation layer directly contacting the uppermost surface of the source, the uppermost surface of the drain, the substrate and the gate foot.