Electronic device
AssigneePlastic Logic Limited
InventorsCatherine Mary Ramsdale, Henning Sirringhaus, Timothy Allan Von Werne
Life of this patent
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Abstract
A technique for high-resolution surface energy assisted patterning of semiconductor active layer islands on top of an array of predefined source-drain electrodes without requiring an additional process step for surface energy patterning.
Claims33
A method of forming an electronic device including spaced apart bodies of electrically conductive material connected by a channel of semiconductive material, the method including the steps of:
- forming said spaced apart bodies of electrically conductive material on a substrate;
- and using said bodies to control the deposition of a liquid including said semiconductive material or a precursor thereto to form said semiconductive channel wherein said electrically conductive bodies are formed by depositing conductive material or a precursor thereto on the substrate, and then removing selected portions of the deposited conductive material or precursor thereto.
A method of forming an electronic device including spaced apart bodies of electrically conductive material connected by a channel of semiconductive material, the method including the steps of:
- forming said spaced apart bodies of electrically conductive material on a substrate;
- forming on the substrate at least one structure in addition to said spaced apart bodies of said electrically conductive material;
- and
- using said bodies to control the deposition of a liquid including said semiconductive material or a precursor thereto to form said semiconductive channel;
- wherein said at least one structure facilitates the deposition of said liquid on the substrate in the space between said two electrically conductive spaced-apart bodies.
Dependencies are inferred from the claim text.