Fractional-N phase locked loop

A phase-locked loop (PLL), configured to receive a reference signal, comprising:

• a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal;
• a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal;
• and
• a fractional frequency divider configured to arrange the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π, wherein the fractional frequency divider is configured to generate the divided feedback signal by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs, and
• wherein a phase offset of the first voltage controlled oscillator output is lesser than a phase offset of the second voltage controlled oscillator output.

A phase-locked loop (PLL), configured to receive a reference signal, comprising:

• a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal;
• a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal;
• and
• a fractional frequency divider configured to arrange the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π, wherein the fractional frequency divider is configured to generate at least one of a first fractional value and a second fractional value by switching among the plurality of voltage controlled oscillator outputs, and to dither a divide value of the fractional frequency divider between the first fractional value and the second fractional value to produce the divided feedback signal.

A phase-locked loop (PLL), configured to receive a reference signal, comprising:

• a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal;
• a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal;
• means for arranging the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π;
• and
• means for generating the divided feedback signal by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs,
• wherein a phase offset of the first voltage controlled oscillator output is greater than a phase offset of the second voltage controlled oscillator output.

A phase-locked loop (PLL), configured to receive a reference signal, comprising:

• a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal;
• a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal;
• means for arranging the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π;
• and
• means for generating the divided feedback signal by switching from a first voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs to a second voltage controlled oscillator output from the plurality of voltage controlled oscillator outputs,
• wherein a phase offset of the first voltage controlled oscillator output is lesser than a phase offset of the second voltage controlled oscillator output.

A method to phase lock a corresponding output of a voltage controlled oscillator having a plurality of voltage controlled oscillator outputs to a reference signal, the method comprises the steps of:

• comparing a divided feedback signal to the reference signal to produce an error signal;
• adjusting a frequency of a voltage controlled oscillator based upon the error signal until the frequency of the voltage controlled oscillator is matched to the reference signal;
• arranging the plurality of voltage controlled oscillator outputs in one or more pairs of voltage controlled oscillator outputs, each voltage controlled oscillator output from the one or more pairs being substantially offset in phase by π, and
• generating the divided feedback signal by switching among the plurality of voltage controlled oscillator outputs.

A phase-locked loop (PLL), configured to receive a reference signal, comprising:

• a phase detector configured to output an error signal based on a difference between a divided feedback signal and the reference signal;
• a voltage controlled oscillator configured to output a plurality of voltage controlled oscillator outputs based on the error signal;
• and
• a fractional frequency divider configured to select among one or more pairs of voltage controlled oscillator outputs from the plurality of voltage controlled oscillator outputs to generate the divided feedback signal, each pair of voltage controlled oscillator outputs including a first voltage controlled oscillator output and a second voltage controlled oscillator output.