Semiconductor device with seal ring

A semiconductor device, comprising:

• a first insulating layer;
• a second insulating layer including a low dielectric constant film of which a relative dielectric constant is less than 3.5;
• a third insulating layer;
• a semiconductor substrate;
• a seal ring formed in closed loop form in a plan view;
• a sacrifice pattern which is a structure in wall-form;
• and
• a fourth insulating layer which is made of SiN, includes a planar portion and a ridged portion and covers said third insulating layer, said seal ring and said sacrifice pattern, wherein
• said semiconductor substrate, said first insulating layer, said second insulating layer and said third insulating layer are layered in order of said semiconductor substrate, said first insulating layer, said second insulating layer, said third insulating layer, respectively,
• said seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate,
• said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip,
• said seal ring protrusion portion protrudes toward a center of said chip between said first insulating layer and said low dielectric constant film,
• said sacrifice pattern is provided outside of said seal ring protrusion portion from said center of the chip, and
• said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer,
• and wherein
• the planar portion of said fourth insulating layer is formed above said sacrifice pattern and the ridged portion of fourth insulating layer covers a top of said seal ring and a part of a side wall of said seal ring.

A semiconductor device, comprising:

• a semiconductor substrate;
• a first insulating layer formed over said semiconductor substrate;
• a second insulating layer including a low dielectric constant film having a relative dielectric constant less than 3.5, said second insulating layer formed over said first insulating layer;
• a third insulating layer formed over said second insulating layer;
• a seal ring formed in closed loop form in a plan view;
• a sacrifice pattern which is a structure in wall-form;
• and
• a fourth insulating layer which is made of a SiN, includes a planar portion and a ridged portion and covers said third insulating layer, said seal ring and said sacrifice pattern, wherein
• said seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate,
• said seal ring includes a first side formed along a first chip end surface, a second side formed approximately in parallel to a second chip end surface, a third side formed approximately in parallel to said first chip end surface, and a fourth side formed along a second chip end surface in a vicinity of a chip corner, said first chip end surface and said second chip end surface forming said chip corner, said second side formed between said first side and said third side, and said third side formed between said second side and said fourth side,
• one end of said first side is electrically coupled to one end of said second side, another end of said second side is electrically coupled to one end of said third side, and another end of said third side is electrically coupled to one end of said fourth side, and
• said first side, said second side, said third side, and said fourth side are formed between said first insulating layer and said low dielectric constant film, and wherein said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer,
• wherein said sacrifice pattern is provided outside of said second side and said third side from center of a semiconductor chip, and
• wherein the planar portion of said fourth insulating layer is formed above said sacrifice pattern and the ridged portion of fourth insulating layer covers a top of said seal ring and a part of a side wall of said seal ring.

A semiconductor device, comprising:

• a chip;
• and
• a low dielectric constant film having a relative dielectric constant less than 3.5 and a seal ring which is a moisture blocking wall in closed loop form in a plan view, wherein
• the seal ring includes a seal ring protrusion portion in inward protruding form in the vicinity of a corner of the chip,
• the seal ring comprising 16 lengths arranged to circumscribe a center point of a surface of said chip, with length 1 connected to length 2, length 2 connected to length 3, length 3 connected to length 4, length 4 connected to length 5, length 5 connected to length 6, length 6 connected to length 7, length 7 connected to length 8, length 8 connected to length 9, length 9 connected to length 10, length 10 connected to length 11, length 11 connected to length 12, length 12 connected to length 13, length 13 connected to length 14, length 14 connected to length 15, length 15 connected to length 16, and length 16 connected to length 1, and
• length 1 is parallel to length 9, length 5 is parallel to length 13, length 3 is parallel to length 11, length 7 is parallel to length 15, length 2 is parallel to length 16, length 4 is parallel to length 6, length 8 is parallel to length 10, and length 12 is parallel to length 14, wherein
• a sacrifice pattern which is a structure in wall form for preventing progress of a crack is provided outside of said sealing protrusion portion from the center of the chip, wherein
• a passivation film covers said low dielectric constant film, said seal ring and said sacrifice pattern and includes a planar portion and a ridged portion, and wherein
• the planar portion of said passivation film is formed above said sacrifice pattern and the ridged portion of said passivation film covers on top of said seal ring and a part of a side wall of said seal ring.