Analytic structure for failure analysis of semiconductor device having a multi-stacked interconnection structure

An analytic structure for failure analysis of a semiconductor device, comprising:

• first and second analytic regions arranged in a semiconductor substrate;
• first and second array structures arranged in the first and second analytic regions, respectively, and the first and second array structures comprising a plurality of semiconductor transistors;
• and
• first and second interconnection structures formed respectively on the first and second analytic regions to connect the semiconductor transistors, each of the first and second interconnection structures comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns,
• wherein each of the first and second interconnection structures has a weak portion, in which the metal patterns and the plugs are formed through a predetermined process having a standard process margin, wherein the metal patterns and plugs of the other portions within the analytic region are formed through a predetermined process having a large process margin relative to the standard process margin, and the weak portions of the first and second interconnection structures are formed at different levels with respect to each other.