US 7,598,562 B2Granted

Semiconductor device and method of manufacturing the same

AssigneeKabushiki Kaisha Toshiba

InventorsHajime Nagano, Takeo Furuhata

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Abstract

A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined on the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes a gate insulating film formed on a surface of the element forming region; a floating gate formed over the gate insulating film; an inter-gate insulating film formed integrally so as to cover the floating gate and the insulating film of the element isolation region and having high dielectric constant in a portion corresponding to the floating gate and low dielectric constant in a portion corresponding to the insulating film of the element isolation region; and a control gate stacked over the floating gate via the inter-gate insulating film.

Claims9

Dependent claims

A semiconductor device, comprising:

a semiconductor substrate including a first upper surface having an element forming region and an element isolation region being adjacent to the element forming region, the element isolation region having a trench;
an element insulating film formed in the trench, including a second upper surface being higher than the first upper surface of the semiconductor substrate in the element forming region and a first side surface protruding from the first upper surface;
a gate insulating film formed on the first upper surface of the semiconductor substrate in the element forming region;
a floating gate electrode formed on the gate insulating film, including a third upper surface being higher than the second upper surface related to the first upper surface, a lower side surface facing to the first side surface and an upper side surface exposed from the element insulating film;
an inter-gate insulating film formed on the third upper surface and the upper side surface of the floating gate electrode and the second upper surface of the element insulating film, the inter-gate insulating film including a first portion located on the third upper surface of the floating gate electrode and a second portion located on the second upper surface of the element insulating film;
and
a control gate electrode formed on the inter-gate insulating film,
wherein the first portion of the inter-gate insulating film includes a silicon nitride film and the second portion of the inter-gate insulating film includes a silicon oxide film that does not contain a nitride.

5 more elements

Dependencies are inferred from the claim text.