Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

A complementary metal oxide semiconductor (CMOS) structure comprising:

• a semiconductor substrate;
• at least one nMOS device located on one region of said semiconductor substrate;
• and
• at least one pMOS device located on another region of said semiconductor substrate, where said at least one nMOS device includes a gate stack comprising at least one elemental metal selected from the group consisting of Ti, La, Y, Hf Ta, Nb, Zr and V and an in-situ metallic capping layer selected from the group consisting of TiN, TaSiN, TiAlN and TaAlN, and said at least one pMOS includes a gate stack comprising at least one elemental metal selected from the group consisting of Re, W, Ni and Ir, and a metallic capping layer selected from the group consisting of TiN, TaSiN, TiAlN and TaAlN, wherein a surface oxide layer is present between the element metal and the metallic capping layer of the at least one pMOS, wherein the surface oxide layer is not present between the element metal and the in-situ metallic capping layer of the nMOS.