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US 7,598,522 B2Granted
Semiconductor substrate and production process thereof
AssigneeFujitsu Microelectronics Limited
InventorsTetsuo Yaegashi, Kouichi Nagai
Life of this patent
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AssigneeFujitsu Microelectronics Limited
InventorsTetsuo Yaegashi, Kouichi Nagai
Estimating the term…
A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitoring pattern, the first film-thickness monitoring pattern and the first pattern group having a third area occupation ratio on the surface, while the second film-thickness monitoring pattern and the second pattern group having a fourth area occupation ratio on the surface, wherein the third area occupation ratio is different from the fourth area occupation ratio.
A semiconductor substrate, comprising:
A semiconductor substrate, comprising:
A semiconductor substrate, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Marks applied to devices
Marks applied to devices, e.g. for alignment or identification: for use before dicing
For use before dicing: located in scribe lines
Generic packages, interconnections, connectors or other constructional details of devices covered by
Term ended 19 May 2024 (estimated)
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The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a ferroelectric film.
Semiconductor storage devices called DRAMs or SRAMs are used extensively as high speed main memory device in information processing apparatuses including computer. However, these devices are volatile storage devices and the information stored therein is lost when the power supply is turned off. In view of this, non-volatile magnetic disk devices have been used as large-capacity auxiliary storage devices for storing programs and data.
However, a magnetic disk unit is mechanically fragile and has problems such as large electric power consumption and slow access speed at the time of reading and writing information.
FIG. 1 is a diagram showing the construction of a conventional FeRAM in a cross-sectional view;
FIGS. 2A-2F are diagrams showing the fabrication process of the FeRAM of FIG. 1;
FIG. 3 is a diagram showing a semiconductor wafer including chip regions of FeRAM in a plan view;
FIG. 6 is a plan view diagram showing a part 100 of a semiconductor wafer according to an embodiment of the present invention.
Referring to FIG. 6, there are formed plural chip regions 100A, 100B, 100 C . . . , on a semiconductor wafer 100 by scribe lines 101, and each chip region includes a memory cell region in which a large number of FeRAMs, each having a construction similar to that of FIG. 1, are formed, wherein it should be noted that there exist, on the wafer 100, chip regions of different area occupation ratios for the ferroelectric capacitors. In the illustrated example, there exist a chip region with the area occupation ratio of 30%, a chip region with the area occupation ratio of 50%, and the chip region with the area occupation ratio of 80%.
Here, it should be noted that “area occupation ratio” is defined as the ratio of the area occupied by plural ferroelectric capacitors in a chip region defined by the scribe lines 101 to the area of the chip region.