Semiconductor process for removing defects due to edge chips of a semiconductor wafer and semiconductor device fabricated thereby

A semiconductor device produced by a process comprising:

• forming a molding layer over a semiconductor wafer;
• etching the molding layer, using a first photoresist pattern on the molding layer as an etching mask, to form a plurality of storage node holes, wherein the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area;
• forming first and second storage nodes in the first and second storage node holes, respectively, wherein the first and second storage nodes have a cylindrical shape;
• filling the first and second cylindrical storage nodes with sacrificial layer patterns;
• removing the sacrificial layer patterns in the first cylindrical storage nodes when the molding layer is etched
• forming a second photoresist pattern on the molding layer that covers the edge chip area;
• and
• selectively etching the molding layer, using the second photoresist pattern as an etching mask, to expose portions of the first storage nodes.

A semiconductor device produced by a process comprising:

• forming a molding layer over a semiconductor wafer;
• etching the molding layer, using a first photoresist pattern on the molding layer as an etching mask, to form a plurality of storage node holes, wherein the plurality of storage node holes include at least one first storage node hole formed on an effective chip area and at least one second storage node hole formed on an edge chip area;
• forming first and second storage nodes in the first and second storage node holes, respectively;
• forming a second photoresist pattern on the molding layer that covers the edge chip area;
• selectively etching the molding layer, using the second photoresist pattern as an etching mask, to expose portions of the first storage nodes;
• removing the second photoresist pattern;
• sequentially forming a dielectric layer and a plate conductive layer overlying the first and second storage nodes;
• and
• patterning the plate conductive layer and the dielectric layer to form plate electrodes and dielectric layer patterns.