Semiconductor memory device and a method of manufacturing the same
AssigneeRenesas Technology Corp.
InventorsMasahiro Moniwa, Hiraku Chakihara, Kousuke Okuyama, Yasuhiko Takahashi
Life of this patent
Estimating the term…
Abstract
A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.
Claims22
A method of manufacturing a semiconductor device including memory cells having MISFETs, comprising steps of:
- (a) forming a first film over a conductive film formed over a main surface of a semiconductor substrate;
- (b) patterning the first film to form first patterns each having a shape extending in a first direction;
- (c) patterning the first patterns in a second direction perpendicular to the first direction to form second patterns each separated in the first direction;
- and
- (d) patterning the conductive film by using the second patterns to form gate electrodes of the MISFETs.
A method of manufacturing a semiconductor device including memory cells having MISFETs, comprising steps of:
- (a) forming a first film over a conductive film formed over a main surface of a semiconductor substrate;
- (b) patterning the first film to form first patterns each having a shape extending in a first direction;
- (c) patterning the first patterns in a second direction perpendicular to the first direction to form second patterns each separated in the first direction;
- and
- (d) patterning the conductive film by using the second patterns to form gate electrodes of the MISFETs,
- wherein each of the memory cells constitutes a memory cell of a static random access memory,
- wherein the memory cell includes a first MISFET and a second MISFET such that the first MISFET and the second MISFET are cross-coupled, and
- wherein the first MISFET and the second MISFET are arranged with point symmetry with respect to a centerpoint in a memory cell forming region.
A method of manufacturing a semiconductor device including memory cells having MISFETs, comprising steps of:
- (a) forming a first film over a conductive film formed over a main surface of a semiconductor substrate;
- (b) patterning the first film to form first patterns each having a shape extending in a first direction;
- (c) patterning the first patterns in a second direction perpendicular to the first direction to form second patterns each separated in the first direction;
- and
- (d) patterning the conductive film by using the second patterns to form gate electrode patterns of the MISFETs,
- wherein each of the memory cells constitutes a memory cell of a static random access memory,
- wherein the memory cell includes a first MISFET and a second MISFET, and
- wherein the gate electrode patterns of the MISFETs have, respectively, a rectangle shape such that a width, in the first direction, of the rectangle shape is greater than a width, in the second direction, of the rectangle shape.
Dependencies are inferred from the claim text.