Semiconductor device having well with peak impurity concentrations and method for fabricating the same
AssigneeFujitsu Microelectronics Limited
InventorYoshihiro Takao
Life of this patent
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Abstract
The semiconductor device comprises a well 58 formed in a semiconductor substrate 10 and having a channel region; a gate electrode 34n formed over the channel region with an insulating film 32 interposed therebetween; source/drain regions 60 formed in the well 58 on both sides of the gate electrode 34n, sandwiching the channel region; and a pocket region 40 formed between the source/drain region and the channel region. The well 58 has a first peak of an impurity concentration at a depth deeper than the pocket region 40 and shallower than the bottom of the source/drain regions 60, and a second peak of the impurity concentration at a depth near the bottom of the source/drain regions 60.
Claims16
A semiconductor device comprising:
- a well of a first conductivity type formed in a semiconductor substrate and having a channel region;
- a gate electrode formed over the channel region with an insulating film interposed therebetween;
- source/drain regions of a second conductivity type formed in the well on both sides of the gate electrode, sandwiching the channel region;
- and
- a pocket region of the first conductivity type formed between at least one of the source/drain regions and the channel region,
- the well having a first peak of an impurity concentration of first impurities of the first conductivity type at a first depth deeper than the pocket region and shallower than the bottom of the source/drain regions, and a second peak of the impurity concentration of second impurities of the first conductivity type at a second depth near the bottom of the source/drain regions.
A semiconductor device including a logic unit and a memory unit, comprising:
- a well of a first conductivity type formed in a semiconductor substrate of the logic unit and having a channel region;
- and
- a logic transistor including a gate electrode formed over the channel region with an insulating film interposed therebetween, source/drain regions of a second conductivity type formed in the well on both sides of the gate electrode, sandwiching the channel region, and a pocket region of the first conductivity type formed between at least one of the source/drain regions and the channel region,
- the well having a first peak of an impurity concentration of first impurities of the first conductivity type at a first depth deeper than the pocket region and shallower than the bottom of the source/drain regions, and a second peak of the impurity concentration of second impurities of the first conductivity type at a second depth near the bottom of the source/drain regions.
A semiconductor device including a low-voltage transistor region and a high-voltage transistor region, comprising:
- a well of a first conductivity type formed in a semiconductor substrate of the low-voltage transistor region and having a channel region;
- and
- a low-voltage transistor including a gate electrode formed over the channel region with an insulating film interposed therebetween, source/drain regions of a second conductivity type formed in the well on both sides of the gate electrode, sandwiching the channel region, and a pocket region of the first conductivity type formed between at least one of the source/drain regions and the channel region,
- the well having a first peak of an impurity concentration of first impurities of the first conductivity type at a first depth deeper than the pocket region and shallower than the bottom of the source/drain regions, and a second peak of the impurity concentration of second impurities of the first conductivity type at a second depth near the bottom of the source/drain regions.
A method for fabricating a semiconductor device, including a well of a first conductivity type formed in a semiconductor substrate and having a channel region, a gate electrode formed over the channel region with an insulating film interposed therebetween, source/drain regions of a second conductivity type formed in the well on both sides of the gate electrode, sandwiching the channel region, and a pocket region of the first conductivity type formed between at least one of the source/drain regions and the channel region, the step of forming the well comprising the steps of:
- forming a first impurity diffused region having a first peak of an impurity concentration of first impurities of the first conductivity type at a first depth deeper than the pocket region and shallower than the bottom of the source/drain regions;
- and
- forming a second impurity diffused region having a second peak of the impurity concentration of second impurities of the first conductivity type at a second depth near the bottom of the source/drain regions.
Dependencies are inferred from the claim text.