Multi-bit memory technology (MMT) and cells

#As the process development has matured and technology has scaled to smaller and smaller dimensions, the Poly-silicon floating gate cell is approaching its scaling limitations, multi-bit storage in a single memory cell has become the norm. The use of a Nitride layer or a silicon-nodule layer capable of location specific charge storage with no spreading, allows easy implementation of multi-bit technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element. If charge is stored in layer of discrete silicon-nodules separated by a thin insulating film, an Oxide silicon-nodule Oxide storage element is used as the storage layer.

#The multi-bit cells proposed are programmed by hot electron programming and erased either by using high Voltage tunneling, or by use of a lower voltage MIM Metal-Insulator-Metal Diode carrier generation method and technology called the Tunnel-Gun or TG.

#This invention relates to the structure and method of Programmable/Erasable multi-bit Non-Volatile Memory cell technology for data storage applications.

#FIG. 1. Cross section along the diffusions of a Prior art NROM or Mirror Bit cell storing two bits of data

#FIG. 2. Cross section through the storage element across the cell of the Prior art NROM or Mirror Bit cell in FIG. 1.

#FIG. 3. Cross section along the diffusions of a MMT-1 cell, a two bit programmable cell with optimized select/program elements and storage element having external diffusion contacts.

#Prior Art Mirror Bit Cell (FIG. 1, and FIG. 2) 1. Diffusion 1 (S/D) 1a. Diffusion 2 (S/D) 3. Channel 4. Oxide (SiO2) 5. Well diffusion in Silicon 6. Nitride layer or Silicon-nodule layer 7. Oxide Note: Layer 4,6 and 7 together form an ONO layer or in the alternate case the OsnO layer. 8. Isolation 9. Poly Silicon layer Control gate 10. Location of storage of Bit 1 11. Location of Storage of Bit 2 Disclosed Multi-bit Memory Technology Cells

#MMT-1 Cell, (FIG. 3, and FIG. 4) MMT-2 Cell, (FIG. 5 and FIG. 6), MMT-3, (FIG. 7 and FIG. 8), MMT-4 Cell, (FIG. 9 and FIG. 10) MMT-5, (FIG. 11 and FIG. 12), MMT-6, (FIG. 13) and MMT-8, (FIG. 15) Note.1: In the case of MIM erase cell MMT-3, the Control gate is replaced by the MIM stack comprising of Collection Grid electrode, Barrier layer and the Injector Electrode. Note.2: Each number with letter combination denotes an element REGION in the cell. 1. Well in Silicon Substrate 2. 2x. Diffusions 3. 3x. Isolation Oxide 4. 4a, 4b, 4c, 4d. 4m. 4n. Integrated channel under each element 5. 5b, 5d. 5n Gate oxide 5a. 5c. 5m. Silicon Dioxide on silicon (2nd oxide of the ONO or OsnO storage element) 6a. 6c. 6m Silicon Nitride Storage layer or alternately silicon-nodule layer (Nitride storage layer of ONO storage element) 7a. 7c. 7m. Silicon Dioxide (1st oxide of the ONO or OsnO storage element) 8a. 8c. 8m. Control element (control gate layer) 9. 9b. 9d. 9n Select/Program element (select/program gate layer) 10a. 1st bit storage location 11a. 2nd bit storage location 10c. '3rd bit storage location 11c. 4th bit storage location 10m. mth bit storage location. 11m. (m+1)th bit storage location. 18a. 18c. 18m. Collection Grid electrode of MIM (bottom layer of MIM stack) 19a. 19c. 19m. Barrier (middle layer of MIM stack) 20a. 20c. 20m. Injector electrode (top layer of MIM stack)

#MMT-7 Cell, FIG. 14 1. Well in Silicon Substrate 2. 2x. Diffusion 3. 3x. Isolation Oxide 4. 4a, 4b, 4c, 4d. 4m. 4n. Integrated channel under each element 5. Silicon Dioxide on silicon (2nd oxide of the ONO storage element) 6. Silicon Nitride Storage layer (Nitride storage layer of the ONO storage element) 7. Silicon Dioxide (Nitride Oxide) (1st oxide of the ONO storage element) 8a. 8c. 8m. Control element (control gate layer) 9. 9b. 9d. 9n Select/Program element (select/program gate layer) 10a. 1st bit storage location 11a. 2nd bit storage location 11c. 3rd bit storage location 11c. 4th bit storage location 10m. mth bit storage location. 11m. (m+1)th bit storage location.