Frequency-division circuit
AssigneeNXP B.V.
InventorJohannes H. A. Brekelmans
Life of this patent
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Abstract
A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA(1), . . . , SA(N); SB(1), . . . , SB(N)). One multi-state circuit (MSCA) switches to a next state in response to a rising edge (Er) in an input signal (OS). The other multi-state circuit (MSCB) switches to a next state in response to a falling edge (Ef) in the input signal (OS). Each multi-state circuit (MSCA, MSCB) has at least one state (SA(1), SB(1)) in which the multi-state circuit inhibits the other multi-state circuit (MSCB, MSCA) so as to prevent the other multi-state circuit from switching to the next state.
Claims12
A frequency-division circuit comprising a pair of multi-state circuits being arranged to provide respective signals that transition at different frequency-divided rates and being arranged to be switched throughout a cycle of states, one multi-state circuit being arranged to switch to a next state in response to a rising edge in an input signal, the other multi-state circuit being arranged to switch to a next state in response to a falling edge in the input signal each multi-state circuit having at least one state in which the multi-state circuit inhibits the other multi-state circuit so as to prevent the other multi-state circuit from switching to the next state.
A method of frequency division that employs a pair of multi-state circuits, the method comprising:
- a rising-edge state-switching step in which one multi-state circuit switches throughout a cycle of states the one multi-state circuit switching to a next state in response to a rising edge in an input signal the one multi-state circuit having at least one state in which the other multi-state circuit is prevented from switching state;
- and
- a falling-edge state-switching step in which the other multi-state circuit switches throughout a cycle of states the other multi-state circuit switching to a next state in response to a falling edge in the input signal the other multi-state circuit having at least one state in which the one multi-state circuit is prevented from switching state, wherein each of the multi-state circuits provide respective signals that transition at different frequency-divided rates.
A signal processing arrangement comprising:
- a frequency-division circuit having
- a pair of multi-state circuits, each being arranged to
- provide respective signals that transition at different frequency-divided rates,
- be switched throughout a cycle of states in response to a rising edge in an input signal,
- switch to a next state in response to an opposing-direction transition edge of the input signal, relative to the direction of the transition edge to which the other of the pair of multi-state circuits responds, and
- mitigate power consumption by operating in at least one state in which the multi-state circuit inhibits the other multi-state circuit from switching to the next state;
- an oscillator circuit for providing an oscillator signal that constitutes the input signal of the frequency-division circuit;
- a mixer-driver circuit for deriving a mixer signal from the pair of multi-state circuits;
- and
- a mixer circuit for mixing a signal to be processed with the mixer signal, wherein each of the multi-state circuits is arranged for providing respective signals that transition at different frequency-divided rates.
Dependencies are inferred from the claim text.