Methods for manufacturing SOI substrate using wafer bonding and complementary high voltage bipolar transistor using the SOI substrate

A SOI structure made by the method comprising:

• providing a first substrate with a first device region containing a first lightly doped impurity region containing a first highly doped impurity region therein and a second device region containing a second lightly doped impurity region containing a second highly doped impurity region therein;
• forming two substantially similar first trenches between the first and second device regions in the first substrate, wherein the depth of the first trenches is deeper than the highly doped impurity regions and shallower than the lightly doped impurity regions;
• forming two substantially similar second trenches in the first trenches by forming an insulating layer on the surfaces of the first trenches;
• forming a polycrystalline silicon layer to fill the second trenches;
• forming a second insulating layer on the polycrystalline silicon layer;
• providing a second substrate on the second insulating layer;
• removing a portion of the first substrate to expose the first insulating layer;
• and forming a first device in the first device region and forming a second device in the second region, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors.

A semiconductor device made by the method comprising:

• providing a first substrate with a first device region containing a first lightly doped impurity region containing a first highly doped impurity region therein and a second device region containing a second lightly doped impurity region containing a second highly doped impurity region therein;
• forming two substantially similar first trenches between the first and second device regions in the first substrate, wherein the depth of the first trenches is deeper than the highly doped impurity regions and shallower than the lightly doped impurity regions;
• forming two substantially similar second trenches in the first trenches by forming an insulating layer on the surfaces of the first trenches;
• providing a second substrate on the insulating layer;
• removing a portion of the first substrate sufficient to expose the first trenches;
• and forming a first device in the first device region and forming a second device in the second region, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors.

A semiconductor device made by the method comprising:

• providing a first substrate with a first device region containing a first lightly doped impurity region containing a first highly doped impurity region therein and a second device region containing a second lightly doped impurity region containing a second highly doped impurity region therein;
• forming two substantially similar first trenches between the first and second device regions in the first substrate, wherein the depth of the first trenches is deeper than the highly doped impurity regions and shallower than the lightly doped impurity regions;
• forming two substantially similar second trenches in the first trenches by forming an insulating layer on the surfaces of the first trenches;
• forming a polycrystalline silicon layer to fill the second trenches;
• forming a second insulating layer on the polycrystalline silicon layer;
• providing a second substrate on the second insulating layer;
• removing a portion of the first substrate to expose the first insulating layer;
• and forming a first device in the first device region and forming a second device in the second region, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors.

An SOI structure comprising:

• a substrate not containing an epitaxial layer;
• a first device in a first device region with a first dopant region containing an upper region having a low concentration of a first impurity and a lower region having a high concentration of a first impurity, wherein the first dopant region forms part of a PNP transistor;
• a second device in a second device region with a second dopant region containing an upper region having a low concentration of a second impurity and a lower region having a high concentration of a second impurity, wherein the second region forms part of a NPN transistor;
• and
• an insulating region isolating the substrate, first device region, and second device region, the insulating region comprising two substantially similar adjacent trenches containing a polysilicon layer;
• wherein the first device and the second device are adjacent each other and comprise a complementary bipolar transistor device.

A SOI structure, comprising:

• a substrate not containing an epitaxial layer;
• a first device in a first device region with a first dopant region containing an upper region having a low concentration of a first impurity and a lower region having a high concentration of a first impurity;
• a second device in a second device region with a second dopant region containing an upper region having a low concentration of a second impurity and a lower region having a high concentration of a second impurity, wherein the first device and the second device are adjacent each other and comprise complimentary bipolar transistors;
• and
• an insulating region isolating the substrate, first device region, and second device region, the insulating region containing a conductive layer within two substantially similar adjacent trenches.