Back to results
US 7,564,284 B2Granted
Time delay circuit and time to digital converter
AssigneeInfineon Technologies AG
InventorsStephan Henzler, Siegmar Köppe, Dominik Lorenz
Life of this patent
Estimating the term…
Abstract
A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.
Claims28
A time delay circuit, comprising:
- a first delay line comprising with a first delay circuit and at least a second delay circuit connected downstream thereto;
- a second delay line comprising a third delay circuit and at least a fourth delay circuit connected downstream thereto;
- and
- at least a first interpolation circuit coupled between an output of the first delay circuit and an output of the fourth delay circuit, and configured to provide at least a first intermediate signal derived by delayed signals in the first and second delay line.
1 more element
A time to digital converter, comprising:
- a plurality of delay circuits connected in series, wherein the delay circuits each comprise an inverting signal characteristic;
- a plurality of latches, wherein each latch is connected to one delay circuit of the plurality of delay circuits, and configured to provide a respective bit value in response to a reference signal;
- at least a first interpolation circuit coupled to an output of a first delay circuit of the plurality of delay circuits and to an output of a second circuit of the plurality of delay circuits, wherein signals at the outputs of the respective first and second delay circuits comprise substantially the same static but delayed logic level, wherein the interpolation circuit is configured to provide at least a first intermediate signal derived by the signals at the outputs of the respective first and second delay circuits;
- and
- a latch coupled the at least first interpolation circuit, and configured to provide an intermediate bit value derived by the at least first intermediate signal in response to the reference signal.
2 more elements
A time to digital converter, comprising:
- a delay circuitry to provide signals having a clock edge, wherein the signals are complementary to each other, the delay circuitry comprising a first pair of delay circuits and at least a second pair of delay circuits connected downstream to the first pair;
- an interpolation circuit arranged between an output terminal of the first pair of delay circuits and an output terminal of the second pair of delay circuits, and configured to provide at least a first delayed intermediate signal, wherein the delayed intermediate signal is derived by clock edges of the delayed signals;
- and
- latch circuits coupled to the output terminals of the first pair and the second pair and to the interpolation circuit.
1 more element
Dependencies are inferred from the claim text.